Hexagon HVX (target/hexagon) import macro definitions
Imported from the Hexagon architecture library
imported/allext_macros.def Top level macro include for all extensions
imported/macros.def Scalar core macros (some HVX here)
imported/mmvec/macros.def HVX macro definitions
The macro definition files specify instruction attributes that are applied
to each instruction that reverences the macro.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson
parent
64458f4855
commit
e3d143e98e
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@ -0,0 +1,25 @@
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Top level file for all instruction set extensions
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*/
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#define EXTNAME mmvec
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#define EXTSTR "mmvec"
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#include "mmvec/macros.def"
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#undef EXTNAME
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#undef EXTSTR
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@ -176,6 +176,12 @@ DEF_MACRO(
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(A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY)
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)
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DEF_MACRO(
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fVSATUVALN,
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({ ((VAL) < 0) ? 0 : ((1LL<<(N))-1);}),
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()
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)
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DEF_MACRO(
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fSATUVALN,
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({fSET_OVERFLOW(); ((VAL) < 0) ? 0 : ((1LL<<(N))-1);}),
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@ -188,6 +194,12 @@ DEF_MACRO(
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()
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)
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DEF_MACRO(
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fVSATVALN,
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({((VAL) < 0) ? (-(1LL<<((N)-1))) : ((1LL<<((N)-1))-1);}),
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()
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)
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DEF_MACRO(
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fZXTN, /* macro name */
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((VAL) & ((1LL<<(N))-1)),
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@ -205,6 +217,11 @@ DEF_MACRO(
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((fSXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATVALN(N,VAL)),
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()
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)
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DEF_MACRO(
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fVSATN,
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((fSXTN(N,64,VAL) == (VAL)) ? (VAL) : fVSATVALN(N,VAL)),
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()
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)
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DEF_MACRO(
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fADDSAT64,
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@ -234,6 +251,12 @@ DEF_MACRO(
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()
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)
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DEF_MACRO(
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fVSATUN,
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((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fVSATUVALN(N,VAL)),
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()
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)
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DEF_MACRO(
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fSATUN,
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((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATUVALN(N,VAL)),
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@ -253,6 +276,19 @@ DEF_MACRO(
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()
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)
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DEF_MACRO(
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fVSATH,
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(fVSATN(16,VAL)),
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()
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)
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DEF_MACRO(
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fVSATUH,
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(fVSATUN(16,VAL)),
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()
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)
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DEF_MACRO(
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fSATUB,
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(fSATUN(8,VAL)),
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@ -265,6 +301,20 @@ DEF_MACRO(
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)
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DEF_MACRO(
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fVSATUB,
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(fVSATUN(8,VAL)),
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()
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)
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DEF_MACRO(
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fVSATB,
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(fVSATN(8,VAL)),
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()
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)
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/*************************************/
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/* immediate extension */
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/*************************************/
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@ -556,6 +606,18 @@ DEF_MACRO(
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/* optional attributes */
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)
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DEF_MACRO(
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fCAST2_2s, /* macro name */
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((size2s_t)(A)),
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/* optional attributes */
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)
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DEF_MACRO(
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fCAST2_2u, /* macro name */
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((size2u_t)(A)),
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/* optional attributes */
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)
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DEF_MACRO(
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fCAST4_4s, /* macro name */
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((size4s_t)(A)),
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@ -876,6 +938,11 @@ DEF_MACRO(
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(((size8s_t)(A))<<N),
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/* optional attributes */
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)
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DEF_MACRO(
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fVSATW, /* saturating to 32-bits*/
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fVSATN(32,((long long)A)),
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()
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)
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DEF_MACRO(
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fSATW, /* saturating to 32-bits*/
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@ -883,6 +950,12 @@ DEF_MACRO(
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()
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)
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DEF_MACRO(
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fVSAT, /* saturating to 32-bits*/
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fVSATN(32,(A)),
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()
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)
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DEF_MACRO(
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fSAT, /* saturating to 32-bits*/
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fSATN(32,(A)),
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@ -1389,6 +1462,11 @@ DEF_MACRO(fSETBITS,
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/*************************************/
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/* Used for parity, etc........ */
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/*************************************/
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DEF_MACRO(fCOUNTONES_2,
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count_ones_2(VAL),
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/* nothing */
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)
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DEF_MACRO(fCOUNTONES_4,
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count_ones_4(VAL),
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/* nothing */
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@ -1419,6 +1497,11 @@ DEF_MACRO(fCL1_4,
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/* nothing */
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)
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DEF_MACRO(fCL1_2,
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count_leading_ones_2(VAL),
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/* nothing */
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)
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DEF_MACRO(fINTERLEAVE,
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interleave(ODD,EVEN),
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/* nothing */
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@ -1576,3 +1659,8 @@ DEF_MACRO(fBRANCH_SPECULATE_STALL,
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},
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()
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)
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DEF_MACRO(IV1DEAD,
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,
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()
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)
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|
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@ -0,0 +1,842 @@
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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DEF_MACRO(fDUMPQ,
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do {
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printf(STR ":" #REG ": 0x%016llx\n",REG.ud[0]);
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} while (0),
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()
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)
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DEF_MACRO(fUSE_LOOKUP_ADDRESS_BY_REV,
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PROC->arch_proc_options->mmvec_use_full_va_for_lookup,
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()
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)
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DEF_MACRO(fUSE_LOOKUP_ADDRESS,
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1,
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()
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)
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DEF_MACRO(fNOTQ,
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({mmqreg_t _ret = {0}; int _i_; for (_i_ = 0; _i_ < fVECSIZE()/64; _i_++) _ret.ud[_i_] = ~VAL.ud[_i_]; _ret;}),
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()
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)
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DEF_MACRO(fGETQBITS,
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((MASK) & (REG.w[(BITNO)>>5] >> ((BITNO) & 0x1f))),
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()
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)
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DEF_MACRO(fGETQBIT,
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fGETQBITS(REG,1,1,BITNO),
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()
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)
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DEF_MACRO(fGENMASKW,
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(((fGETQBIT(QREG,(IDX*4+0)) ? 0xFF : 0x0) << 0)
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|((fGETQBIT(QREG,(IDX*4+1)) ? 0xFF : 0x0) << 8)
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|((fGETQBIT(QREG,(IDX*4+2)) ? 0xFF : 0x0) << 16)
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|((fGETQBIT(QREG,(IDX*4+3)) ? 0xFF : 0x0) << 24)),
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()
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)
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DEF_MACRO(fGET10BIT,
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{
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COE = (((((fGETUBYTE(3,VAL) >> (2 * POS)) & 3) << 8) | fGETUBYTE(POS,VAL)) << 6);
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COE >>= 6;
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},
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()
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)
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DEF_MACRO(fVMAX,
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(X>Y) ? X : Y,
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()
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)
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DEF_MACRO(fGETNIBBLE,
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( fSXTN(4,8,(SRC >> (4*IDX)) & 0xF) ),
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()
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)
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DEF_MACRO(fGETCRUMB,
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( fSXTN(2,8,(SRC >> (2*IDX)) & 0x3) ),
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()
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)
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DEF_MACRO(fGETCRUMB_SYMMETRIC,
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( (fGETCRUMB(IDX,SRC)>=0 ? (2-fGETCRUMB(IDX,SRC)) : fGETCRUMB(IDX,SRC) ) ),
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()
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)
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#define ZERO_OFFSET_2B +
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DEF_MACRO(fGENMASKH,
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(((fGETQBIT(QREG,(IDX*2+0)) ? 0xFF : 0x0) << 0)
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|((fGETQBIT(QREG,(IDX*2+1)) ? 0xFF : 0x0) << 8)),
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()
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)
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DEF_MACRO(fGETMASKW,
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(VREG.w[IDX] & fGENMASKW((QREG),IDX)),
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()
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)
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DEF_MACRO(fGETMASKH,
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(VREG.h[IDX] & fGENMASKH((QREG),IDX)),
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()
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)
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DEF_MACRO(fCONDMASK8,
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(fGETQBIT(QREG,IDX) ? (YESVAL) : (NOVAL)),
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()
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)
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DEF_MACRO(fCONDMASK16,
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((fGENMASKH(QREG,IDX) & (YESVAL)) | (fGENMASKH(fNOTQ(QREG),IDX) & (NOVAL))),
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()
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)
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DEF_MACRO(fCONDMASK32,
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((fGENMASKW(QREG,IDX) & (YESVAL)) | (fGENMASKW(fNOTQ(QREG),IDX) & (NOVAL))),
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()
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)
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DEF_MACRO(fSETQBITS,
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do {
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size4u_t __TMP = (VAL);
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REG.w[(BITNO)>>5] &= ~((MASK) << ((BITNO) & 0x1f));
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REG.w[(BITNO)>>5] |= (((__TMP) & (MASK)) << ((BITNO) & 0x1f));
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} while (0),
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()
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)
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DEF_MACRO(fSETQBIT,
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fSETQBITS(REG,1,1,BITNO,VAL),
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()
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)
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DEF_MACRO(fVBYTES,
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(fVECSIZE()),
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()
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)
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DEF_MACRO(fVHALVES,
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(fVECSIZE()/2),
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()
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)
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DEF_MACRO(fVWORDS,
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(fVECSIZE()/4),
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()
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)
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DEF_MACRO(fVDWORDS,
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(fVECSIZE()/8),
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()
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)
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DEF_MACRO(fVALIGN,
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( ADDR = ADDR & ~(LOG2_ALIGNMENT-1)),
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()
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)
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DEF_MACRO(fVLASTBYTE,
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( ADDR = ADDR | (LOG2_ALIGNMENT-1)),
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()
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)
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DEF_MACRO(fVELEM,
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((fVECSIZE()*8)/WIDTH),
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()
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)
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DEF_MACRO(fVECLOGSIZE,
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(mmvec_current_veclogsize(thread)),
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()
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)
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DEF_MACRO(fVECSIZE,
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(1<<fVECLOGSIZE()),
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()
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)
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DEF_MACRO(fSWAPB,
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{
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size1u_t tmp = A;
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A = B;
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B = tmp;
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},
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/* NOTHING */
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)
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DEF_MACRO(
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fVZERO,
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mmvec_zero_vector(),
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()
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)
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DEF_MACRO(
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fNEWVREG,
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((THREAD2STRUCT->VRegs_updated & (((VRegMask)1)<<VNUM)) ? THREAD2STRUCT->future_VRegs[VNUM] : mmvec_zero_vector()),
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(A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY)
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)
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DEF_MACRO(
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fV_AL_CHECK,
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if ((EA) & (MASK)) {
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warn("aligning misaligned vector. PC=%08x EA=%08x",thread->Regs[REG_PC],(EA));
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},
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()
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)
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DEF_MACRO(fSCATTER_INIT,
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{
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mem_vector_scatter_init(thread, insn, REGION_START, LENGTH, ELEMENT_SIZE);
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if (EXCEPTION_DETECTED) return;
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},
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(A_STORE,A_MEMLIKE,A_RESTRICT_SLOT0ONLY)
|
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)
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DEF_MACRO(fGATHER_INIT,
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{
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mem_vector_gather_init(thread, insn, REGION_START, LENGTH, ELEMENT_SIZE);
|
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if (EXCEPTION_DETECTED) return;
|
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},
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(A_LOAD,A_MEMLIKE,A_RESTRICT_SLOT1ONLY)
|
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)
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DEF_MACRO(fSCATTER_FINISH,
|
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{
|
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if (EXCEPTION_DETECTED) return;
|
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mem_vector_scatter_finish(thread, insn, OP);
|
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},
|
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()
|
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)
|
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|
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DEF_MACRO(fGATHER_FINISH,
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{
|
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if (EXCEPTION_DETECTED) return;
|
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mem_vector_gather_finish(thread, insn);
|
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},
|
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()
|
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)
|
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|
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|
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DEF_MACRO(CHECK_VTCM_PAGE,
|
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{
|
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int slot = insn->slot;
|
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paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
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pa = pa & ~(ALIGNMENT-1);
|
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FLAG = (pa < (thread->mem_access[slot].paddr+LENGTH));
|
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},
|
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()
|
||||
)
|
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DEF_MACRO(COUNT_OUT_OF_BOUNDS,
|
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{
|
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if (!FLAG)
|
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{
|
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THREAD2STRUCT->vtcm_log.oob_access += SIZE;
|
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warn("Scatter/Gather out of bounds of region");
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}
|
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},
|
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()
|
||||
)
|
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|
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DEF_MACRO(fLOG_SCATTER_OP,
|
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{
|
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// Log the size and indicate that the extension ext.c file needs to increment right before memory write
|
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THREAD2STRUCT->vtcm_log.op = 1;
|
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THREAD2STRUCT->vtcm_log.op_size = SIZE;
|
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},
|
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()
|
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)
|
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|
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|
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|
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DEF_MACRO(fVLOG_VTCM_WORD_INCREMENT,
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{
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int slot = insn->slot;
|
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int log_bank = 0;
|
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int log_byte =0;
|
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paddr_t pa = thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMENT-1));
|
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paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
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for(int i0 = 0; i0 < 4; i0++)
|
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{
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log_byte = ((OFFSET>=0)&&((pa+i0)<=pa_high));
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log_bank |= (log_byte<<i0);
|
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LOG_VTCM_BYTE(pa+i0,log_byte,INC.ub[4*IDX+i0],4*IDX+i0);
|
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}
|
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{ LOG_VTCM_BANK(pa, log_bank, IDX); }
|
||||
},
|
||||
()
|
||||
)
|
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|
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DEF_MACRO(fVLOG_VTCM_HALFWORD_INCREMENT,
|
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{
|
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int slot = insn->slot;
|
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int log_bank = 0;
|
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int log_byte = 0;
|
||||
paddr_t pa = thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMENT-1));
|
||||
paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
|
||||
for(int i0 = 0; i0 < 2; i0++) {
|
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log_byte = ((OFFSET>=0)&&((pa+i0)<=pa_high));
|
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log_bank |= (log_byte<<i0);
|
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LOG_VTCM_BYTE(pa+i0,log_byte,INC.ub[2*IDX+i0],2*IDX+i0);
|
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}
|
||||
{ LOG_VTCM_BANK(pa, log_bank,IDX); }
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fVLOG_VTCM_HALFWORD_INCREMENT_DV,
|
||||
{
|
||||
int slot = insn->slot;
|
||||
int log_bank = 0;
|
||||
int log_byte = 0;
|
||||
paddr_t pa = thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMENT-1));
|
||||
paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
|
||||
for(int i0 = 0; i0 < 2; i0++) {
|
||||
log_byte = ((OFFSET>=0)&&((pa+i0)<=pa_high));
|
||||
log_bank |= (log_byte<<i0);
|
||||
LOG_VTCM_BYTE(pa+i0,log_byte,INC.ub[2*IDX+i0],2*IDX+i0);
|
||||
}
|
||||
{ LOG_VTCM_BANK(pa, log_bank,(2*IDX2+IDX_H));}
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
|
||||
|
||||
DEF_MACRO(GATHER_FUNCTION,
|
||||
{
|
||||
int slot = insn->slot;
|
||||
int i0;
|
||||
paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
|
||||
paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
|
||||
int log_bank = 0;
|
||||
int log_byte = 0;
|
||||
for(i0 = 0; i0 < ELEMENT_SIZE; i0++)
|
||||
{
|
||||
log_byte = ((OFFSET>=0)&&((pa+i0)<=pa_high)) && QVAL;
|
||||
log_bank |= (log_byte<<i0);
|
||||
size1u_t B = sim_mem_read1(thread->system_ptr, thread->threadId, thread->mem_access[slot].paddr+OFFSET+i0);
|
||||
THREAD2STRUCT->tmp_VRegs[0].ub[ELEMENT_SIZE*IDX+i0] = B;
|
||||
LOG_VTCM_BYTE(pa+i0,log_byte,B,ELEMENT_SIZE*IDX+i0);
|
||||
}
|
||||
LOG_VTCM_BANK(pa, log_bank,BANK_IDX);
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
|
||||
|
||||
DEF_MACRO(fVLOG_VTCM_GATHER_WORD,
|
||||
{
|
||||
GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 4, IDX, 1);
|
||||
},
|
||||
()
|
||||
)
|
||||
DEF_MACRO(fVLOG_VTCM_GATHER_HALFWORD,
|
||||
{
|
||||
GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, IDX, 1);
|
||||
},
|
||||
()
|
||||
)
|
||||
DEF_MACRO(fVLOG_VTCM_GATHER_HALFWORD_DV,
|
||||
{
|
||||
GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, (2*IDX2+IDX_H), 1);
|
||||
},
|
||||
()
|
||||
)
|
||||
DEF_MACRO(fVLOG_VTCM_GATHER_WORDQ,
|
||||
{
|
||||
GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 4, IDX, fGETQBIT(QsV,4*IDX+i0));
|
||||
},
|
||||
()
|
||||
)
|
||||
DEF_MACRO(fVLOG_VTCM_GATHER_HALFWORDQ,
|
||||
{
|
||||
GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, IDX, fGETQBIT(QsV,2*IDX+i0));
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fVLOG_VTCM_GATHER_HALFWORDQ_DV,
|
||||
{
|
||||
GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, (2*IDX2+IDX_H), fGETQBIT(QsV,2*IDX+i0));
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
|
||||
DEF_MACRO(DEBUG_LOG_ADDR,
|
||||
{
|
||||
|
||||
if (thread->processor_ptr->arch_proc_options->mmvec_network_addr_log2)
|
||||
{
|
||||
|
||||
int slot = insn->slot;
|
||||
paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
|
||||
}
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
DEF_MACRO(SCATTER_OP_WRITE_TO_MEM,
|
||||
{
|
||||
for (int i = 0; i < mmvecx->vtcm_log.size; i+=sizeof(TYPE))
|
||||
{
|
||||
if ( mmvecx->vtcm_log.mask.ub[i] != 0) {
|
||||
TYPE dst = 0;
|
||||
TYPE inc = 0;
|
||||
for(int j = 0; j < sizeof(TYPE); j++) {
|
||||
dst |= (sim_mem_read1(thread->system_ptr, thread->threadId, mmvecx->vtcm_log.pa[i+j]) << (8*j));
|
||||
inc |= mmvecx->vtcm_log.data.ub[j+i] << (8*j);
|
||||
|
||||
mmvecx->vtcm_log.mask.ub[j+i] = 0;
|
||||
mmvecx->vtcm_log.data.ub[j+i] = 0;
|
||||
mmvecx->vtcm_log.offsets.ub[j+i] = 0;
|
||||
}
|
||||
dst += inc;
|
||||
for(int j = 0; j < sizeof(TYPE); j++) {
|
||||
sim_mem_write1(thread->system_ptr,thread->threadId, mmvecx->vtcm_log.pa[i+j], (dst >> (8*j))& 0xFF );
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(SCATTER_FUNCTION,
|
||||
{
|
||||
int slot = insn->slot;
|
||||
int i0;
|
||||
paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
|
||||
paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
|
||||
int log_bank = 0;
|
||||
int log_byte = 0;
|
||||
for(i0 = 0; i0 < ELEMENT_SIZE; i0++) {
|
||||
log_byte = ((OFFSET>=0)&&((pa+i0)<=pa_high)) && QVAL;
|
||||
log_bank |= (log_byte<<i0);
|
||||
LOG_VTCM_BYTE(pa+i0,log_byte,IN.ub[ELEMENT_SIZE*IDX+i0],ELEMENT_SIZE*IDX+i0);
|
||||
}
|
||||
LOG_VTCM_BANK(pa, log_bank,BANK_IDX);
|
||||
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fVLOG_VTCM_HALFWORD,
|
||||
{
|
||||
SCATTER_FUNCTION (EA,OFFSET,IDX, LEN, 2, IDX, 1, IN);
|
||||
},
|
||||
()
|
||||
)
|
||||
DEF_MACRO(fVLOG_VTCM_WORD,
|
||||
{
|
||||
SCATTER_FUNCTION (EA,OFFSET,IDX, LEN, 4, IDX, 1, IN);
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fVLOG_VTCM_HALFWORDQ,
|
||||
{
|
||||
SCATTER_FUNCTION (EA,OFFSET,IDX, LEN, 2, IDX, fGETQBIT(QsV,2*IDX+i0), IN);
|
||||
},
|
||||
()
|
||||
)
|
||||
DEF_MACRO(fVLOG_VTCM_WORDQ,
|
||||
{
|
||||
SCATTER_FUNCTION (EA,OFFSET,IDX, LEN, 4, IDX, fGETQBIT(QsV,4*IDX+i0), IN);
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
DEF_MACRO(fVLOG_VTCM_HALFWORD_DV,
|
||||
{
|
||||
SCATTER_FUNCTION (EA,OFFSET,IDX, LEN, 2, (2*IDX2+IDX_H), 1, IN);
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fVLOG_VTCM_HALFWORDQ_DV,
|
||||
{
|
||||
SCATTER_FUNCTION (EA,OFFSET,IDX, LEN, 2, (2*IDX2+IDX_H), fGETQBIT(QsV,2*IDX+i0), IN);
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
DEF_MACRO(fSTORERELEASE,
|
||||
{
|
||||
fV_AL_CHECK(EA,fVECSIZE()-1);
|
||||
|
||||
mem_store_release(thread, insn, fVECSIZE(), EA&~(fVECSIZE()-1), EA, TYPE, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
},
|
||||
(A_STORE,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fVFETCH_AL,
|
||||
{
|
||||
fV_AL_CHECK(EA,fVECSIZE()-1);
|
||||
mem_fetch_vector(thread, insn, EA&~(fVECSIZE()-1), insn->slot, fVECSIZE());
|
||||
},
|
||||
(A_LOAD,A_MEMLIKE)
|
||||
)
|
||||
|
||||
|
||||
DEF_MACRO(fLOADMMV_AL,
|
||||
{
|
||||
fV_AL_CHECK(EA,ALIGNMENT-1);
|
||||
thread->last_pkt->double_access_vec = 0;
|
||||
mem_load_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &DST.ub[0], LEN, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
},
|
||||
(A_LOAD,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fLOADMMV,
|
||||
fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST),
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fLOADMMVQ,
|
||||
do {
|
||||
int __i;
|
||||
fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST);
|
||||
fVFOREACH(8,__i) if (!fGETQBIT(QVAL,__i)) DST.b[__i] = 0;
|
||||
} while (0),
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fLOADMMVNQ,
|
||||
do {
|
||||
int __i;
|
||||
fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST);
|
||||
fVFOREACH(8,__i) if (fGETQBIT(QVAL,__i)) DST.b[__i] = 0;
|
||||
} while (0),
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fLOADMMVU_AL,
|
||||
{
|
||||
size4u_t size2 = (EA)&(ALIGNMENT-1);
|
||||
size4u_t size1 = LEN-size2;
|
||||
thread->last_pkt->double_access_vec = 1;
|
||||
mem_load_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot */ 1, size2, &DST.ub[size1], size2, fUSE_LOOKUP_ADDRESS());
|
||||
mem_load_vector_oddva(thread, insn, EA, EA,/* slot */ 0, size1, &DST.ub[0], size1, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
},
|
||||
(A_LOAD,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fLOADMMVU,
|
||||
{
|
||||
/* if address happens to be aligned, only do aligned load */
|
||||
thread->last_pkt->pkt_has_vtcm_access = 0;
|
||||
thread->last_pkt->pkt_access_count = 0;
|
||||
if ( (EA & (fVECSIZE()-1)) == 0) {
|
||||
thread->last_pkt->pkt_has_vmemu_access = 0;
|
||||
thread->last_pkt->double_access = 0;
|
||||
|
||||
fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST);
|
||||
} else {
|
||||
thread->last_pkt->pkt_has_vmemu_access = 1;
|
||||
thread->last_pkt->double_access = 1;
|
||||
|
||||
fLOADMMVU_AL(EA,fVECSIZE(),fVECSIZE(),DST);
|
||||
}
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMV_AL,
|
||||
{
|
||||
fV_AL_CHECK(EA,ALIGNMENT-1);
|
||||
mem_store_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &SRC.ub[0], 0, 0, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
},
|
||||
(A_STORE,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMV,
|
||||
fSTOREMMV_AL(EA,fVECSIZE(),fVECSIZE(),SRC),
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVQ_AL,
|
||||
do {
|
||||
mmvector_t maskvec;
|
||||
int i;
|
||||
for (i = 0; i < fVECSIZE(); i++) maskvec.ub[i] = fGETQBIT(MASK,i);
|
||||
mem_store_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &SRC.ub[0], &maskvec.ub[0], 0, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
} while (0),
|
||||
(A_STORE,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVQ,
|
||||
fSTOREMMVQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK),
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVNQ_AL,
|
||||
{
|
||||
mmvector_t maskvec;
|
||||
int i;
|
||||
for (i = 0; i < fVECSIZE(); i++) maskvec.ub[i] = fGETQBIT(MASK,i);
|
||||
fV_AL_CHECK(EA,ALIGNMENT-1);
|
||||
mem_store_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot, LEN, &SRC.ub[0], &maskvec.ub[0], 1, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
},
|
||||
(A_STORE,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVNQ,
|
||||
fSTOREMMVNQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK),
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVU_AL,
|
||||
{
|
||||
size4u_t size1 = ALIGNMENT-((EA)&(ALIGNMENT-1));
|
||||
size4u_t size2;
|
||||
if (size1>LEN) size1 = LEN;
|
||||
size2 = LEN-size1;
|
||||
mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot */ 1, size2, &SRC.ub[size1], 0, 0, fUSE_LOOKUP_ADDRESS());
|
||||
mem_store_vector_oddva(thread, insn, EA, EA, /* slot */ 0, size1, &SRC.ub[0], 0, 0, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
},
|
||||
(A_STORE,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVU,
|
||||
{
|
||||
thread->last_pkt->pkt_has_vtcm_access = 0;
|
||||
thread->last_pkt->pkt_access_count = 0;
|
||||
if ( (EA & (fVECSIZE()-1)) == 0) {
|
||||
thread->last_pkt->double_access = 0;
|
||||
fSTOREMMV_AL(EA,fVECSIZE(),fVECSIZE(),SRC);
|
||||
} else {
|
||||
thread->last_pkt->double_access = 1;
|
||||
thread->last_pkt->pkt_has_vmemu_access = 1;
|
||||
fSTOREMMVU_AL(EA,fVECSIZE(),fVECSIZE(),SRC);
|
||||
}
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVQU_AL,
|
||||
{
|
||||
size4u_t size1 = ALIGNMENT-((EA)&(ALIGNMENT-1));
|
||||
size4u_t size2;
|
||||
mmvector_t maskvec;
|
||||
int i;
|
||||
for (i = 0; i < fVECSIZE(); i++) maskvec.ub[i] = fGETQBIT(MASK,i);
|
||||
if (size1>LEN) size1 = LEN;
|
||||
size2 = LEN-size1;
|
||||
mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(),/* slot */ 1, size2, &SRC.ub[size1], &maskvec.ub[size1], 0, fUSE_LOOKUP_ADDRESS());
|
||||
mem_store_vector_oddva(thread, insn, EA, /* slot */ 0, size1, &SRC.ub[0], &maskvec.ub[0], 0, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
},
|
||||
(A_STORE,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVQU,
|
||||
{
|
||||
thread->last_pkt->pkt_has_vtcm_access = 0;
|
||||
thread->last_pkt->pkt_access_count = 0;
|
||||
if ( (EA & (fVECSIZE()-1)) == 0) {
|
||||
thread->last_pkt->double_access = 0;
|
||||
fSTOREMMVQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK);
|
||||
} else {
|
||||
thread->last_pkt->double_access = 1;
|
||||
thread->last_pkt->pkt_has_vmemu_access = 1;
|
||||
fSTOREMMVQU_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK);
|
||||
}
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVNQU_AL,
|
||||
{
|
||||
size4u_t size1 = ALIGNMENT-((EA)&(ALIGNMENT-1));
|
||||
size4u_t size2;
|
||||
mmvector_t maskvec;
|
||||
int i;
|
||||
for (i = 0; i < fVECSIZE(); i++) maskvec.ub[i] = fGETQBIT(MASK,i);
|
||||
if (size1>LEN) size1 = LEN;
|
||||
size2 = LEN-size1;
|
||||
mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot */ 1, size2, &SRC.ub[size1], &maskvec.ub[size1], 1, fUSE_LOOKUP_ADDRESS());
|
||||
mem_store_vector_oddva(thread, insn, EA, EA, /* slot */ 0, size1, &SRC.ub[0], &maskvec.ub[0], 1, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr));
|
||||
},
|
||||
(A_STORE,A_MEMLIKE)
|
||||
)
|
||||
|
||||
DEF_MACRO(fSTOREMMVNQU,
|
||||
{
|
||||
thread->last_pkt->pkt_has_vtcm_access = 0;
|
||||
thread->last_pkt->pkt_access_count = 0;
|
||||
if ( (EA & (fVECSIZE()-1)) == 0) {
|
||||
thread->last_pkt->double_access = 0;
|
||||
fSTOREMMVNQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK);
|
||||
} else {
|
||||
thread->last_pkt->double_access = 1;
|
||||
thread->last_pkt->pkt_has_vmemu_access = 1;
|
||||
fSTOREMMVNQU_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK);
|
||||
}
|
||||
},
|
||||
()
|
||||
)
|
||||
|
||||
|
||||
|
||||
|
||||
DEF_MACRO(fVFOREACH,
|
||||
for (VAR = 0; VAR < fVELEM(WIDTH); VAR++),
|
||||
/* NOTHING */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVARRAY_ELEMENT_ACCESS,
|
||||
ARRAY.v[(INDEX) / (fVECSIZE()/(sizeof(ARRAY.TYPE[0])))].TYPE[(INDEX) % (fVECSIZE()/(sizeof(ARRAY.TYPE[0])))],
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fVNEWCANCEL,
|
||||
do { THREAD2STRUCT->VRegs_select &= ~(1<<(REGNUM)); } while (0),
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fTMPVDATA,
|
||||
mmvec_vtmp_data(thread),
|
||||
(A_CVI)
|
||||
)
|
||||
|
||||
DEF_MACRO(fVSATDW,
|
||||
fVSATW( ( ( ((long long)U)<<32 ) | fZXTN(32,64,V) ) ),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVASL_SATHI,
|
||||
fVSATW(((U)<<1) | ((V)>>31)),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVUADDSAT,
|
||||
fVSATUN( WIDTH, fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V)),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVSADDSAT,
|
||||
fVSATN( WIDTH, fSXTN(WIDTH, 2*WIDTH, U) + fSXTN(WIDTH, 2*WIDTH, V)),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVUSUBSAT,
|
||||
fVSATUN( WIDTH, fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V)),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVSSUBSAT,
|
||||
fVSATN( WIDTH, fSXTN(WIDTH, 2*WIDTH, U) - fSXTN(WIDTH, 2*WIDTH, V)),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVAVGU,
|
||||
((fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V))>>1),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVAVGURND,
|
||||
((fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V)+1)>>1),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVNAVGU,
|
||||
((fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V))>>1),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVNAVGURNDSAT,
|
||||
fVSATUN(WIDTH,((fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V)+1)>>1)),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVAVGS,
|
||||
((fSXTN(WIDTH, 2*WIDTH, U) + fSXTN(WIDTH, 2*WIDTH, V))>>1),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVAVGSRND,
|
||||
((fSXTN(WIDTH, 2*WIDTH, U) + fSXTN(WIDTH, 2*WIDTH, V)+1)>>1),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVNAVGS,
|
||||
((fSXTN(WIDTH, 2*WIDTH, U) - fSXTN(WIDTH, 2*WIDTH, V))>>1),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVNAVGSRND,
|
||||
((fSXTN(WIDTH, 2*WIDTH, U) - fSXTN(WIDTH, 2*WIDTH, V)+1)>>1),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVNAVGSRNDSAT,
|
||||
fVSATN(WIDTH,((fSXTN(WIDTH, 2*WIDTH, U) - fSXTN(WIDTH, 2*WIDTH, V)+1)>>1)),
|
||||
/* attribs */
|
||||
)
|
||||
|
||||
|
||||
DEF_MACRO(fVNOROUND,
|
||||
VAL,
|
||||
/* NOTHING */
|
||||
)
|
||||
DEF_MACRO(fVNOSAT,
|
||||
VAL,
|
||||
/* NOTHING */
|
||||
)
|
||||
|
||||
DEF_MACRO(fVROUND,
|
||||
((VAL) + (((SHAMT)>0)?(1LL<<((SHAMT)-1)):0)),
|
||||
/* NOTHING */
|
||||
)
|
||||
|
||||
DEF_MACRO(fCARRY_FROM_ADD32,
|
||||
(((fZXTN(32,64,A)+fZXTN(32,64,B)+C) >> 32) & 1),
|
||||
/* NOTHING */
|
||||
)
|
||||
|
||||
DEF_MACRO(fUARCH_NOTE_PUMP_4X,
|
||||
,
|
||||
()
|
||||
)
|
||||
|
||||
DEF_MACRO(fUARCH_NOTE_PUMP_2X,
|
||||
,
|
||||
()
|
||||
)
|
||||
Loading…
Reference in New Issue