Provide extNs_M instructions

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
malc 2008-07-23 20:01:23 +00:00
parent 1d58ee9f3b
commit e46b9681e5
4 changed files with 40 additions and 0 deletions

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@ -1339,6 +1339,13 @@ static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out_qemu_st(s, args, 3);
break;
case INDEX_op_ext8s_i32:
tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
break;
case INDEX_op_ext16s_i32:
tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
break;
default:
tcg_dump_ops (s, stderr);
tcg_abort ();
@ -1415,6 +1422,9 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
#endif
{ INDEX_op_ext8s_i32, { "r", "r" } },
{ INDEX_op_ext16s_i32, { "r", "r" } },
{ -1 },
};

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@ -71,6 +71,8 @@ enum {
/* optional instructions */
#define TCG_TARGET_HAS_neg_i32
#define TCG_TARGET_HAS_div_i32
#define TCG_TARGET_HAS_ext8s_i32
#define TCG_TARGET_HAS_ext16s_i32
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24

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@ -969,6 +969,8 @@ void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
const int *const_args)
{
int c;
switch (opc) {
case INDEX_op_exit_tb:
tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
@ -1313,6 +1315,21 @@ static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
tcg_out_qemu_st (s, args, 3);
break;
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
c = EXTSB;
goto gen_ext;
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
c = EXTSH;
goto gen_ext;
case INDEX_op_ext32s_i64:
c = EXTSW;
goto gen_ext;
gen_ext:
tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
break;
default:
tcg_dump_ops (s, stderr);
tcg_abort ();
@ -1404,6 +1421,12 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_st32, { "K", "K" } },
{ INDEX_op_qemu_st64, { "M", "M", "M" } },
{ INDEX_op_ext8s_i32, { "r", "r" } },
{ INDEX_op_ext16s_i32, { "r", "r" } },
{ INDEX_op_ext8s_i64, { "r", "r" } },
{ INDEX_op_ext16s_i64, { "r", "r" } },
{ INDEX_op_ext32s_i64, { "r", "r" } },
{ -1 },
};

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@ -72,6 +72,11 @@ enum {
#define TCG_TARGET_HAS_div_i32
#define TCG_TARGET_HAS_neg_i64
#define TCG_TARGET_HAS_div_i64
#define TCG_TARGET_HAS_ext8s_i32
#define TCG_TARGET_HAS_ext16s_i32
#define TCG_TARGET_HAS_ext8s_i64
#define TCG_TARGET_HAS_ext16s_i64
#define TCG_TARGET_HAS_ext32s_i64
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24