hppa power button support, graphics updates and firmware fixes
-----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCX1aFfQAKCRD3ErUQojoP X9kAAP9UgEFiOVCQILI7TSHl2moEjQ7x31CA/Bmod6V+eVKM6QD9Gucjy0KC5DWe PogywA+CdndMLmH71GN/AFrENVqNnws= =bbqB -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/hdeller/tags/target-hppa-pull-request' into staging hppa power button support, graphics updates and firmware fixes # gpg: Signature made Mon 07 Sep 2020 20:09:49 BST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * remotes/hdeller/tags/target-hppa-pull-request: hw/display/artist: Allow screen size up to 2048 lines hw/display/artist: Refactor x/y coordination extraction hw/display/artist: Verify artist screen resolution target/hppa: Fix boot with old Linux installation CDs hw/hppa: Add power button emulation hw/hppa: Tell SeaBIOS port address of fw_cfg hw/hppa: Change fw_cfg port address hw/hppa: Store boot device in fw_cfg section hw/hppa: Make number of TLB and BTLB entries configurable seabios-hppa: Update SeaBIOS to hppa-qemu-5.2-2 tag Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
e4c4f7db60
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@ -192,6 +192,10 @@ static const char *artist_reg_name(uint64_t addr)
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}
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#undef REG_NAME
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/* artist has a fixed line length of 2048 bytes. */
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#define ADDR_TO_Y(addr) extract32(addr, 11, 11)
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#define ADDR_TO_X(addr) extract32(addr, 0, 11)
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static int16_t artist_get_x(uint32_t reg)
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{
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return reg >> 16;
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@ -348,13 +352,13 @@ static void artist_invalidate_cursor(ARTISTState *s)
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y, s->cursor_height);
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}
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static void vram_bit_write(ARTISTState *s, int posx, int posy, bool incr_x,
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static void vram_bit_write(ARTISTState *s, int posy, bool incr_x,
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int size, uint32_t data)
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{
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struct vram_buffer *buf;
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uint32_t vram_bitmask = s->vram_bitmask;
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int mask, i, pix_count, pix_length;
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unsigned int offset, width;
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unsigned int posx, offset, width;
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uint8_t *data8, *p;
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pix_count = vram_write_pix_per_transfer(s);
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@ -366,6 +370,8 @@ static void vram_bit_write(ARTISTState *s, int posx, int posy, bool incr_x,
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if (s->cmap_bm_access) {
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offset = s->vram_pos;
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} else {
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posx = ADDR_TO_X(s->vram_pos >> 2);
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posy += ADDR_TO_Y(s->vram_pos >> 2);
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offset = posy * width + posx;
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}
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@ -858,7 +864,6 @@ static void artist_reg_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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ARTISTState *s = opaque;
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int posx, posy;
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int width, height;
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trace_artist_reg_write(size, addr, artist_reg_name(addr & ~3ULL), val);
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@ -881,16 +886,12 @@ static void artist_reg_write(void *opaque, hwaddr addr, uint64_t val,
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break;
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case VRAM_WRITE_INCR_Y:
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posx = (s->vram_pos >> 2) & 0x7ff;
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posy = (s->vram_pos >> 13) & 0x3ff;
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vram_bit_write(s, posx, posy + s->vram_char_y++, false, size, val);
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vram_bit_write(s, s->vram_char_y++, false, size, val);
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break;
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case VRAM_WRITE_INCR_X:
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case VRAM_WRITE_INCR_X2:
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posx = (s->vram_pos >> 2) & 0x7ff;
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posy = (s->vram_pos >> 13) & 0x3ff;
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vram_bit_write(s, posx, posy + s->vram_char_y, true, size, val);
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vram_bit_write(s, s->vram_char_y, true, size, val);
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break;
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case VRAM_IDX:
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@ -1156,8 +1157,7 @@ static void artist_vram_write(void *opaque, hwaddr addr, uint64_t val,
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{
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ARTISTState *s = opaque;
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struct vram_buffer *buf;
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int posy = (addr >> 11) & 0x3ff;
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int posx = addr & 0x7ff;
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unsigned int posy, posx;
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unsigned int offset;
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trace_artist_vram_write(size, addr, val);
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@ -1170,6 +1170,9 @@ static void artist_vram_write(void *opaque, hwaddr addr, uint64_t val,
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}
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buf = vram_write_buffer(s);
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posy = ADDR_TO_Y(addr);
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posx = ADDR_TO_X(addr);
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if (!buf->size) {
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return;
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}
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@ -1212,7 +1215,7 @@ static uint64_t artist_vram_read(void *opaque, hwaddr addr, unsigned size)
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ARTISTState *s = opaque;
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struct vram_buffer *buf;
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uint64_t val;
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int posy, posx;
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unsigned int posy, posx;
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if (s->cmap_bm_access) {
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buf = &s->vram_buffer[ARTIST_BUFFER_CMAP];
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@ -1229,8 +1232,8 @@ static uint64_t artist_vram_read(void *opaque, hwaddr addr, unsigned size)
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return 0;
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}
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posy = (addr >> 13) & 0x3ff;
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posx = (addr >> 2) & 0x7ff;
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posy = ADDR_TO_Y(addr);
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posx = ADDR_TO_X(addr);
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if (posy > buf->height || posx > buf->width) {
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return 0;
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@ -1374,6 +1377,18 @@ static void artist_realizefn(DeviceState *dev, Error **errp)
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struct vram_buffer *buf;
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hwaddr offset = 0;
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if (s->width > 2048 || s->height > 2048) {
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error_report("artist: screen size can not exceed 2048 x 2048 pixel.");
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s->width = MIN(s->width, 2048);
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s->height = MIN(s->height, 2048);
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}
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if (s->width < 640 || s->height < 480) {
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error_report("artist: minimum screen size is 640 x 480 pixel.");
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s->width = MAX(s->width, 640);
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s->height = MAX(s->height, 480);
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}
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memory_region_init(&s->mem_as_root, OBJECT(dev), "artist", ~0ull);
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address_space_init(&s->as, &s->mem_as_root, "artist");
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@ -38,8 +38,7 @@
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#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR)
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#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA)
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/* QEMU fw_cfg interface port */
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#define QEMU_FW_CFG_IO_BASE (MEMORY_HPA + 0x80)
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#define FW_CFG_IO_BASE 0xfffa0000
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#define PORT_SERIAL1 (DINO_UART_HPA + 0x800)
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#define PORT_SERIAL2 (LASI_UART_HPA + 0x800)
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@ -12,6 +12,7 @@
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#include "qemu/error-report.h"
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#include "sysemu/reset.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/runstate.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/timer/i8254.h"
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#include "hw/char/serial.h"
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@ -27,6 +28,30 @@
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#define MIN_SEABIOS_HPPA_VERSION 1 /* require at least this fw version */
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#define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
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static void hppa_powerdown_req(Notifier *n, void *opaque)
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{
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hwaddr soft_power_reg = HPA_POWER_BUTTON;
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uint32_t val;
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val = ldl_be_phys(&address_space_memory, soft_power_reg);
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if ((val >> 8) == 0) {
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/* immediately shut down when under hardware control */
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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return;
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}
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/* clear bit 31 to indicate that the power switch was pressed. */
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val &= ~1;
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stl_be_phys(&address_space_memory, soft_power_reg, val);
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}
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static Notifier hppa_system_powerdown_notifier = {
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.notify = hppa_powerdown_req
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};
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static ISABus *hppa_isa_bus(void)
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{
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ISABus *isa_bus;
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@ -58,12 +83,18 @@ static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr)
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static HPPACPU *cpu[HPPA_MAX_CPUS];
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static uint64_t firmware_entry;
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static FWCfgState *create_fw_cfg(MachineState *ms)
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{
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FWCfgState *fw_cfg;
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uint64_t val;
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fw_cfg = fw_cfg_init_mem(QEMU_FW_CFG_IO_BASE, QEMU_FW_CFG_IO_BASE + 4);
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fw_cfg = fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4);
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fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ram_size);
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@ -72,6 +103,21 @@ static FWCfgState *create_fw_cfg(MachineState *ms)
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fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version",
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g_memdup(&val, sizeof(val)), sizeof(val));
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val = cpu_to_le64(HPPA_TLB_ENTRIES);
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fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries",
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g_memdup(&val, sizeof(val)), sizeof(val));
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val = cpu_to_le64(HPPA_BTLB_ENTRIES);
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fw_cfg_add_file(fw_cfg, "/etc/cpu/btlb_entries",
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g_memdup(&val, sizeof(val)), sizeof(val));
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val = cpu_to_le64(HPA_POWER_BUTTON);
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fw_cfg_add_file(fw_cfg, "/etc/power-button-addr",
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g_memdup(&val, sizeof(val)), sizeof(val));
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fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ms->boot_order[0]);
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qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
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return fw_cfg;
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}
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@ -160,6 +206,9 @@ static void machine_hppa_init(MachineState *machine)
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}
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}
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/* register power switch emulation */
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qemu_register_powerdown_notifier(&hppa_system_powerdown_notifier);
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/* Load firmware. Given that this is not "real" firmware,
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but one explicitly written for the emulation, we might as
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well load it directly from an ELF image. */
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@ -273,6 +322,9 @@ static void machine_hppa_init(MachineState *machine)
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/* tell firmware how many SMP CPUs to present in inventory table */
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cpu[0]->env.gr[21] = smp_cpus;
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/* tell firmware fw_cfg port */
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cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
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}
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static void hppa_machine_reset(MachineState *ms)
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@ -300,6 +352,8 @@ static void hppa_machine_reset(MachineState *ms)
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cpu[0]->env.gr[24] = 'c';
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/* gr22/gr23 unused, no initrd while reboot. */
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cpu[0]->env.gr[21] = smp_cpus;
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/* tell firmware fw_cfg port */
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cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
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}
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Binary file not shown.
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@ -1 +1 @@
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Subproject commit 4ff7639e2b86d5775fa7d5cd0dbfa4d3a385a701
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Subproject commit 73b740f77190643b2ada5ee97a9a108c6ef2a37b
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@ -196,9 +196,12 @@ struct CPUHPPAState {
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target_ureg shadow[7]; /* shadow registers */
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/* ??? The number of entries isn't specified by the architecture. */
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#define HPPA_TLB_ENTRIES 256
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#define HPPA_BTLB_ENTRIES 0
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/* ??? Implement a unified itlb/dtlb for the moment. */
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/* ??? We should use a more intelligent data structure. */
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hppa_tlb_entry tlb[256];
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hppa_tlb_entry tlb[HPPA_TLB_ENTRIES];
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uint32_t tlb_last;
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};
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@ -149,9 +149,9 @@ lci 000001 ----- ----- -- 01001100 0 t:5
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# Arith/Log
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####
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andcm 000010 ..... ..... .... 000000 0 ..... @rrr_cf
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and 000010 ..... ..... .... 001000 0 ..... @rrr_cf
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or 000010 ..... ..... .... 001001 0 ..... @rrr_cf
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andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf
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and 000010 ..... ..... .... 001000 - ..... @rrr_cf
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or 000010 ..... ..... .... 001001 - ..... @rrr_cf
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xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf
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uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf
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ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
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@ -161,13 +161,13 @@ uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf
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dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf
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dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf
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add 000010 ..... ..... .... 0110.. 0 ..... @rrr_cf_sh
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add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh
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add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh
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add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh
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add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0
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add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0
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sub 000010 ..... ..... .... 010000 0 ..... @rrr_cf
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sub 000010 ..... ..... .... 010000 - ..... @rrr_cf
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sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf
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sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf
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sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf
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