target-sparc: Directly implement easy ldd/std asis
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
35e94905ce
commit
e4dc0052a4
@ -1988,6 +1988,7 @@ typedef enum {
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GET_ASI_HELPER,
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GET_ASI_EXCP,
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GET_ASI_DIRECT,
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GET_ASI_DTWINX,
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} ASIType;
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typedef struct {
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@ -2046,18 +2047,26 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
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switch (asi) {
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case ASI_N: /* Nucleus */
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case ASI_NL: /* Nucleus LE */
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case ASI_TWINX_N:
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case ASI_TWINX_NL:
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mem_idx = MMU_NUCLEUS_IDX;
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break;
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case ASI_AIUP: /* As if user primary */
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case ASI_AIUPL: /* As if user primary LE */
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case ASI_TWINX_AIUP:
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case ASI_TWINX_AIUP_L:
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mem_idx = MMU_USER_IDX;
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break;
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case ASI_AIUS: /* As if user secondary */
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case ASI_AIUSL: /* As if user secondary LE */
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case ASI_TWINX_AIUS:
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case ASI_TWINX_AIUS_L:
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mem_idx = MMU_USER_SECONDARY_IDX;
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break;
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case ASI_S: /* Secondary */
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case ASI_SL: /* Secondary LE */
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case ASI_TWINX_S:
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case ASI_TWINX_SL:
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if (mem_idx == MMU_USER_IDX) {
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mem_idx = MMU_USER_SECONDARY_IDX;
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} else if (mem_idx == MMU_KERNEL_IDX) {
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@ -2066,6 +2075,8 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
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break;
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case ASI_P: /* Primary */
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case ASI_PL: /* Primary LE */
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case ASI_TWINX_P:
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case ASI_TWINX_PL:
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break;
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}
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switch (asi) {
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@ -2081,6 +2092,18 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
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case ASI_PL:
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type = GET_ASI_DIRECT;
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break;
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case ASI_TWINX_N:
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case ASI_TWINX_NL:
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case ASI_TWINX_AIUP:
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case ASI_TWINX_AIUP_L:
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case ASI_TWINX_AIUS:
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case ASI_TWINX_AIUS_L:
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case ASI_TWINX_P:
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case ASI_TWINX_PL:
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case ASI_TWINX_S:
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case ASI_TWINX_SL:
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type = GET_ASI_DTWINX;
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break;
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}
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/* The little-endian asis all have bit 3 set. */
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if (asi & 8) {
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@ -2100,6 +2123,9 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
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switch (da.type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DTWINX: /* Reserved for ldda. */
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gen_exception(dc, TT_ILL_INSN);
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break;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
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@ -2137,6 +2163,9 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
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switch (da.type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DTWINX: /* Reserved for stda. */
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gen_exception(dc, TT_ILL_INSN);
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break;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
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@ -2303,32 +2332,59 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
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}
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}
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static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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int insn, int rd)
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static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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{
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DisasASI da = get_asi(dc, insn, MO_TEQ);
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TCGv_i64 hi = gen_dest_gpr(dc, rd);
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TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
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switch (da.type) {
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case GET_ASI_EXCP:
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return;
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case GET_ASI_DTWINX:
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gen_check_align(addr, 15);
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
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break;
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case GET_ASI_DIRECT:
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
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/* Note that LE ldda acts as if each 32-bit register
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result is byte swapped. Having just performed one
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64-bit bswap, we need now to swap the writebacks. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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tcg_gen_extr32_i64(lo, hi, tmp);
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} else {
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tcg_gen_extr32_i64(hi, lo, tmp);
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}
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tcg_temp_free_i64(tmp);
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}
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break;
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default:
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{
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TCGv_i32 r_asi = tcg_const_i32(da.asi);
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TCGv_i64 tmp;
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save_state(dc);
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gen_helper_ldda_asi(cpu_env, addr, r_asi);
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tcg_temp_free_i32(r_asi);
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tmp = gen_dest_gpr(dc, rd);
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tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUSPARCState, qt0.high));
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gen_store_gpr(dc, rd, tmp);
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tmp = gen_dest_gpr(dc, rd + 1);
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tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUSPARCState, qt0.low));
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gen_store_gpr(dc, rd + 1, tmp);
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tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUSPARCState, qt0.high));
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tcg_gen_ld_i64(lo, cpu_env, offsetof(CPUSPARCState, qt0.low));
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}
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break;
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}
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gen_store_gpr(dc, rd, hi);
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gen_store_gpr(dc, rd + 1, lo);
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}
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static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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@ -2340,6 +2396,33 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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switch (da.type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DTWINX:
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gen_check_align(addr, 15);
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
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break;
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case GET_ASI_DIRECT:
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{
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TCGv_i64 t64 = tcg_temp_new_i64();
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/* Note that LE stda acts as if each 32-bit register result is
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byte swapped. We will perform one 64-bit LE store, so now
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we must swap the order of the construction. */
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if ((da.memop & MO_BSWAP) == MO_TE) {
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tcg_gen_concat32_i64(t64, lo, hi);
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} else {
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tcg_gen_concat32_i64(t64, hi, lo);
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}
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
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tcg_temp_free_i64(t64);
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}
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break;
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default:
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{
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TCGv_i32 r_asi = tcg_const_i32(da.asi);
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@ -2379,14 +2462,14 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2,
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}
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#elif !defined(CONFIG_USER_ONLY)
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static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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int insn, int rd)
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static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
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{
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/* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
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whereby "rd + 1" elicits "error: array subscript is above array".
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Since we have already asserted that rd is even, the semantics
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are unchanged. */
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TCGv lo = gen_dest_gpr(dc, rd | 1);
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TCGv hi = gen_dest_gpr(dc, rd);
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TCGv_i64 t64 = tcg_temp_new_i64();
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DisasASI da = get_asi(dc, insn, MO_TEQ);
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@ -2394,6 +2477,10 @@ static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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case GET_ASI_EXCP:
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tcg_temp_free_i64(t64);
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return;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
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break;
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default:
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{
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TCGv_i32 r_asi = tcg_const_i32(da.asi);
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@ -2427,6 +2514,10 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
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switch (da.type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
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break;
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default:
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{
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TCGv_i32 r_asi = tcg_const_i32(da.asi);
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@ -4918,7 +5009,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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if (rd & 1) {
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goto illegal_insn;
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}
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gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
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gen_ldda_asi(dc, cpu_addr, insn, rd);
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goto skip_move;
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case 0x19: /* ldsba, load signed byte alternate */
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gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
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