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target/riscv: Allow debugger to access sstc CSRs 

At present with a debugger attached sstc CSRs can only be accssed
when CPU is in M-mode, or configured correctly.

Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-17-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Bin Meng 2023-02-28 21:45:33 +08:00 committed by Palmer Dabbelt
parent 0308fc6219
commit e4e1f216a1
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
1 changed files with 14 additions and 5 deletions
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19
target/riscv/csr.c
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@ -952,6 +952,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
hmode_check = true;
}
RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
if (env->debugger) {
return RISCV_EXCP_NONE;
}
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
}
@ -972,11 +985,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
}
if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
hmode_check = true;
}
return hmode_check ? hmode(env, csrno) : smode(env, csrno);
return RISCV_EXCP_NONE;
}
static RISCVException sstc_32(CPURISCVState *env, int csrno)