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target/mips: Add field and R/W access to ITU control register ICR0 

Add field and R/W access to ITU control register ICR0.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Yongbok Kim 2019-01-03 15:39:31 +01:00 committed by Aleksandar Markovic
parent 5fb2dcd179
commit e5345d9675
2 changed files with 25 additions and 1 deletions
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22
hw/misc/mips_itu.c
View File

@ -55,9 +55,17 @@ typedef enum ITCView {
ITCVIEW_EF_SYNC = 2,
ITCVIEW_EF_TRY = 3,
ITCVIEW_PV_SYNC = 4,
ITCVIEW_PV_TRY = 5
ITCVIEW_PV_TRY = 5,
ITCVIEW_PV_ICR0 = 15,
} ITCView;
#define ITC_ICR0_CELL_NUM 16
#define ITC_ICR0_BLK_GRAIN 8
#define ITC_ICR0_BLK_GRAIN_MASK 0x7
#define ITC_ICR0_ERR_AXI 2
#define ITC_ICR0_ERR_PARITY 1
#define ITC_ICR0_ERR_EXEC 0
MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
{
return &itu->tag_io;
@ -382,6 +390,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
case ITCVIEW_PV_TRY:
ret = view_pv_try_read(cell);
break;
case ITCVIEW_PV_ICR0:
ret = s->icr0;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"itc_storage_read: Bad ITC View %d\n", (int)view);
@ -417,6 +428,15 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
case ITCVIEW_PV_TRY:
view_pv_try_write(cell);
break;
case ITCVIEW_PV_ICR0:
if (data & 0x7) {
/* clear ERROR bits */
s->icr0 &= ~(data & 0x7);
}
/* set BLK_GRAIN */
s->icr0 &= ~0x700;
s->icr0 |= data & 0x700;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"itc_storage_write: Bad ITC View %d\n", (int)view);

4
include/hw/misc/mips_itu.h
View File

@ -66,6 +66,10 @@ typedef struct MIPSITUState {
/* ITC Configuration Tags */
uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
MemoryRegion tag_io;
/* ITU Control Register */
uint64_t icr0;
} MIPSITUState;
/* Get ITC Configuration Tag memory region. */