heathrow nvram support - use different device ids for different macios
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1511 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -31,7 +31,7 @@
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#define INITRD_LOAD_ADDR 0x01800000
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#define INITRD_LOAD_ADDR 0x01800000
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/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
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/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
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NVRAM (not implemented). */
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NVRAM */
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static int dbdma_mem_index;
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static int dbdma_mem_index;
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static int cuda_mem_index;
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static int cuda_mem_index;
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@ -39,6 +39,7 @@ static int ide0_mem_index = -1;
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static int ide1_mem_index = -1;
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static int ide1_mem_index = -1;
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static int openpic_mem_index = -1;
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static int openpic_mem_index = -1;
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static int heathrow_pic_mem_index = -1;
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static int heathrow_pic_mem_index = -1;
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static int macio_nvram_mem_index = -1;
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/* DBDMA: currently no op - should suffice right now */
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/* DBDMA: currently no op - should suffice right now */
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@ -83,6 +84,53 @@ static CPUReadMemoryFunc *dbdma_read[] = {
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&dbdma_readl,
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&dbdma_readl,
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};
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};
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/* macio style NVRAM device */
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typedef struct MacIONVRAMState {
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uint8_t data[0x2000];
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} MacIONVRAMState;
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static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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MacIONVRAMState *s = opaque;
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addr = (addr >> 4) & 0x1fff;
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s->data[addr] = value;
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// printf("macio_nvram_writeb %04x = %02x\n", addr, value);
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}
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static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
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{
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MacIONVRAMState *s = opaque;
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uint32_t value;
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addr = (addr >> 4) & 0x1fff;
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value = s->data[addr];
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// printf("macio_nvram_readb %04x = %02x\n", addr, value);
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return value;
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}
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static CPUWriteMemoryFunc *macio_nvram_write[] = {
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&macio_nvram_writeb,
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&macio_nvram_writeb,
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&macio_nvram_writeb,
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};
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static CPUReadMemoryFunc *macio_nvram_read[] = {
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&macio_nvram_readb,
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&macio_nvram_readb,
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&macio_nvram_readb,
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};
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static MacIONVRAMState *macio_nvram_init(void)
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{
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MacIONVRAMState *s;
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s = qemu_mallocz(sizeof(MacIONVRAMState));
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if (!s)
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return NULL;
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macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
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macio_nvram_write, s);
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return s;
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}
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static void macio_map(PCIDevice *pci_dev, int region_num,
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static void macio_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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uint32_t addr, uint32_t size, int type)
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{
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{
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@ -100,9 +148,11 @@ static void macio_map(PCIDevice *pci_dev, int region_num,
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cpu_register_physical_memory(addr + 0x40000, 0x40000,
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cpu_register_physical_memory(addr + 0x40000, 0x40000,
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openpic_mem_index);
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openpic_mem_index);
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}
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}
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if (macio_nvram_mem_index >= 0)
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cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
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}
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}
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static void macio_init(PCIBus *bus)
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static void macio_init(PCIBus *bus, int device_id)
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{
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{
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PCIDevice *d;
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PCIDevice *d;
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@ -112,8 +162,8 @@ static void macio_init(PCIBus *bus)
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in PearPC */
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in PearPC */
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d->config[0x00] = 0x6b; // vendor_id
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d->config[0x00] = 0x6b; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x22;
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d->config[0x02] = device_id;
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d->config[0x03] = 0x00;
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d->config[0x03] = device_id >> 8;
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d->config[0x0a] = 0x00; // class_sub = pci2pci
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d->config[0x0a] = 0x00; // class_sub = pci2pci
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d->config[0x0b] = 0xff; // class_base = bridge
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d->config[0x0b] = 0xff; // class_base = bridge
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@ -219,6 +269,28 @@ static void pic_irq_request(void *opaque, int level)
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{
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{
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}
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}
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static uint8_t nvram_chksum(const uint8_t *buf, int n)
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{
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int sum, i;
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sum = 0;
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for(i = 0; i < n; i++)
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sum += buf[i];
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return (sum & 0xff) + (sum >> 8);
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}
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/* set a free Mac OS NVRAM partition */
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void pmac_format_nvram_partition(uint8_t *buf, int len)
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{
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char partition_name[12] = "wwwwwwwwwwww";
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buf[0] = 0x7f; /* free partition magic */
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buf[1] = 0; /* checksum */
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buf[2] = len >> 8;
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buf[3] = len;
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memcpy(buf + 4, partition_name, 12);
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buf[1] = nvram_chksum(buf, 16);
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}
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/* PowerPC CHRP hardware initialisation */
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/* PowerPC CHRP hardware initialisation */
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static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename,
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DisplayState *ds, const char **fd_filename,
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@ -369,7 +441,13 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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adb_kbd_init(&adb_bus);
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adb_kbd_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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macio_init(pci_bus);
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{
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MacIONVRAMState *nvr;
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nvr = macio_nvram_init();
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pmac_format_nvram_partition(nvr->data, 0x2000);
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}
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macio_init(pci_bus, 0x0017);
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
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@ -416,7 +494,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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adb_kbd_init(&adb_bus);
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adb_kbd_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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macio_init(pci_bus);
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macio_init(pci_bus, 0x0022);
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
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