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Another fix for CP0 Cause register handling.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2658 c046a42c-6fe2-441c-8c8c-71466251a162
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ths 2007-04-13 20:17:54 +00:00
parent 5425a2164c
commit e58c8ba5f6
2 changed files with 2 additions and 2 deletions
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2
target-mips/helper.c
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@ -403,7 +403,7 @@ void do_interrupt (CPUState *env)
env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
}
env->PC += offset;
env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
break;
default:
if (logfile) {

2
target-mips/op.c
View File

@ -1401,7 +1401,7 @@ void op_mtc0_cause (void)
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
mask |= 1 << CP0Ca_DC;
env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);
env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
/* Handle the software interrupt as an hardware one, as they
are very similar */