tcg/loongarch64: Introduce prepare_host_addr
Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, tcg_out_zext_addr_if_32_bit, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
7131d3cf72
commit
e63eed328f
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@ -818,81 +818,12 @@ static void * const qemu_st_helpers[4] = {
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[MO_64] = helper_le_stq_mmu,
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};
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/* We expect to use a 12-bit negative offset from ENV. */
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
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static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
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{
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tcg_out_opc_b(s, 0);
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return reloc_br_sd10k16(s->code_ptr - 1, target);
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}
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/*
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* Emits common code for TLB addend lookup, that eventually loads the
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* addend in TCG_REG_TMP2.
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*/
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static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, MemOpIdx oi,
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tcg_insn_unit **label_ptr, bool is_load)
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{
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MemOp opc = get_memop(oi);
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unsigned s_bits = opc & MO_SIZE;
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unsigned a_bits = get_alignment_bits(opc);
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tcg_target_long compare_mask;
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int mem_index = get_mmuidx(oi);
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int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
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int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
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int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
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tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
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tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
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/* Load the tlb comparator and the addend. */
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tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
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is_load ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write));
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
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offsetof(CPUTLBEntry, addend));
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/* We don't support unaligned accesses. */
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if (a_bits < s_bits) {
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a_bits = s_bits;
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}
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/* Clear the non-page, non-alignment bits from the address. */
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compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
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tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
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tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
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/* Compare masked address with the TLB entry. */
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label_ptr[0] = s->code_ptr;
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tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
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/* TLB Hit - addend in TCG_REG_TMP2, ready for use. */
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}
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static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
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TCGType type,
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TCGReg datalo, TCGReg addrlo,
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void *raddr, tcg_insn_unit **label_ptr)
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{
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->oi = oi;
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label->type = type;
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label->datalo_reg = datalo;
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label->datahi_reg = 0; /* unused */
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label->addrlo_reg = addrlo;
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label->addrhi_reg = 0; /* unused */
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label->raddr = tcg_splitwx_to_rx(raddr);
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label->label_ptr[0] = label_ptr[0];
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}
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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MemOpIdx oi = l->oi;
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@ -941,33 +872,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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return tcg_out_goto(s, l->raddr);
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}
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#else
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/*
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* Alignment helpers for user-mode emulation
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*/
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static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg,
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unsigned a_bits)
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{
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TCGLabelQemuLdst *l = new_ldst_label(s);
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l->is_ld = is_ld;
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l->addrlo_reg = addr_reg;
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/*
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* Without micro-architecture details, we don't know which of bstrpick or
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* andi is faster, so use bstrpick as it's not constrained by imm field
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* width. (Not to say alignments >= 2^12 are going to happen any time
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* soon, though)
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*/
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tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
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l->label_ptr[0] = s->code_ptr;
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tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
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l->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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{
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/* resolve label address */
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@ -997,27 +901,102 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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#endif /* CONFIG_SOFTMMU */
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/*
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* `ext32u` the address register into the temp register given,
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* if target is 32-bit, no-op otherwise.
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*
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* Returns the address register ready for use with TLB addend.
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*/
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static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s,
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TCGReg addr, TCGReg tmp)
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{
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if (TARGET_LONG_BITS == 32) {
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tcg_out_ext32u(s, tmp, addr);
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return tmp;
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}
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return addr;
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}
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typedef struct {
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TCGReg base;
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TCGReg index;
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} HostAddress;
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/*
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* For softmmu, perform the TLB load and compare.
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* For useronly, perform any required alignment tests.
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* In both cases, return a TCGLabelQemuLdst structure if the slow path
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* is required and fill in @h with the host address for the fast path.
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*/
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static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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TCGReg addr_reg, MemOpIdx oi,
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bool is_ld)
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{
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TCGLabelQemuLdst *ldst = NULL;
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MemOp opc = get_memop(oi);
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unsigned a_bits = get_alignment_bits(opc);
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#ifdef CONFIG_SOFTMMU
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unsigned s_bits = opc & MO_SIZE;
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int mem_index = get_mmuidx(oi);
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int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
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int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
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int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
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tcg_target_long compare_mask;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addr_reg;
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
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tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
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tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
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/* Load the tlb comparator and the addend. */
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tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
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is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write));
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
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offsetof(CPUTLBEntry, addend));
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/* We don't support unaligned accesses. */
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if (a_bits < s_bits) {
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a_bits = s_bits;
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}
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/* Clear the non-page, non-alignment bits from the address. */
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compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
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tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
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tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg);
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/* Compare masked address with the TLB entry. */
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
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h->index = TCG_REG_TMP2;
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#else
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if (a_bits) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addr_reg;
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/*
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* Without micro-architecture details, we don't know which of
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* bstrpick or andi is faster, so use bstrpick as it's not
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* constrained by imm field width. Not to say alignments >= 2^12
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* are going to happen any time soon.
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*/
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tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
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}
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h->index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
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#endif
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if (TARGET_LONG_BITS == 32) {
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h->base = TCG_REG_TMP0;
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tcg_out_ext32u(s, h->base, addr_reg);
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} else {
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h->base = addr_reg;
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}
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return ldst;
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}
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static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type,
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TCGReg rd, HostAddress h)
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{
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@ -1057,29 +1036,17 @@ static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type,
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static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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MemOpIdx oi, TCGType data_type)
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{
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MemOp opc = get_memop(oi);
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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#ifdef CONFIG_SOFTMMU
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tcg_insn_unit *label_ptr[1];
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ldst = prepare_host_addr(s, &h, addr_reg, oi, true);
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tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h);
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tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
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h.index = TCG_REG_TMP2;
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#else
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, true, addr_reg, a_bits);
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if (ldst) {
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ldst->type = data_type;
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ldst->datalo_reg = data_reg;
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ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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h.index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
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#endif
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h.base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
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tcg_out_qemu_ld_indexed(s, opc, data_type, data_reg, h);
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#ifdef CONFIG_SOFTMMU
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add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
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s->code_ptr, label_ptr);
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#endif
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}
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static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc,
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@ -1109,29 +1076,17 @@ static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc,
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static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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MemOpIdx oi, TCGType data_type)
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{
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MemOp opc = get_memop(oi);
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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#ifdef CONFIG_SOFTMMU
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tcg_insn_unit *label_ptr[1];
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ldst = prepare_host_addr(s, &h, addr_reg, oi, false);
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tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h);
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tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
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h.index = TCG_REG_TMP2;
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#else
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unsigned a_bits = get_alignment_bits(opc);
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if (a_bits) {
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tcg_out_test_alignment(s, false, addr_reg, a_bits);
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if (ldst) {
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ldst->type = data_type;
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ldst->datalo_reg = data_reg;
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ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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h.index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
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#endif
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h.base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
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tcg_out_qemu_st_indexed(s, opc, data_reg, h);
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#ifdef CONFIG_SOFTMMU
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add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
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s->code_ptr, label_ptr);
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#endif
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}
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/*
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