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ppc/xive: Introduce helpers for the NVT id

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Each vCPU in the system is identified with an NVT identifier which is
pushed in the OS CAM line (QW1W2) of the HW thread interrupt context
register when the vCPU is dispatched on a HW thread. This identifier
is used by the presenter subengine to find a matching target to notify
of an event. It is also used to fetch the associate NVT structure
which may contain pending interrupts that need a resend.

Add a couple of helpers for the NVT ids. The NVT space is 19 bits
wide, giving a maximum of 512K per chip.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-11-15 17:24:15 +01:00 committed by David Gibson
parent 516883c2f1
commit e6488eeba8
2 changed files with 21 additions and 5 deletions
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5
include/hw/ppc/xive.h
View File

@ -418,11 +418,6 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);
static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
{
return (nvt_blk << 19) | nvt_idx;
}
/*
* KVM XIVE device helpers
*/

21
include/hw/ppc/xive_regs.h
View File

@ -272,4 +272,25 @@ typedef struct XiveNVT {
#define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
/*
* The VP number space in a block is defined by the END_W6_NVT_INDEX
* field of the XIVE END
*/
#define XIVE_NVT_SHIFT 19
static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
{
return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx;
}
static inline uint32_t xive_nvt_idx(uint32_t cam_line)
{
return cam_line & ((1 << XIVE_NVT_SHIFT) - 1);
}
static inline uint32_t xive_nvt_blk(uint32_t cam_line)
{
return (cam_line >> XIVE_NVT_SHIFT) & 0xf;
}
#endif /* PPC_XIVE_REGS_H */