Extend maximum gvec vector size
Fix i386 avx2 dupi Fix mips host user-only write detection Misc cleanups. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAl9/DDodHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/Nbgf/eHOncxQwA/eAsiJ3 Q79LbjXTEYZUfxpO3vuFwB2ZUvrwBS6daPyIskxRAQRdfAfcWV3hDY5G+tcdZyLr alMuas1bMyb6x+QxVVDbqmKm81Ky8dTCS+NRDGtBWWnJzStTEER29GSPJbHkVNnl IUgPbFdZxVeq1+QwI67ez+hExghirjZK/RoGtO1aU8M5J921v0HZ0rguEc16D3N+ KMh/4/SZ6ai2GNgcqVhJ2SdUpVr+mmpaw4D+/bJaPVn/Hvct1jMYBXJTpl/Tf9Ac FBVZiMDmF3HYSSiEDmzttZiqJwnk+uvaNoN79oJQ/mcXiq6dWkUUG8Eei7KJYwVt noLHew== =NrIp -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20201008' into staging Extend maximum gvec vector size Fix i386 avx2 dupi Fix mips host user-only write detection Misc cleanups. # gpg: Signature made Thu 08 Oct 2020 13:55:22 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20201008: accel/tcg: Fix computing of is_write for MIPS tcg: Remove TCG_TARGET_HAS_cmp_vec tcg/optimize: Fold dup2_vec tcg: Fix generation of dupi_vec for 32-bit host tcg/i386: Fix dupi for avx2 32-bit hosts tcg: Remove TCGOpDef.used tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields tcg: Remove TCG_CT_REG tcg: Move sorted_args into TCGArgConstraint.sort_index tcg: Drop union from TCGArgConstraint tcg: Adjust simd_desc size encoding Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
e64cf4d569
|
@ -702,16 +702,51 @@ int cpu_signal_handler(int host_signum, void *pinfo,
|
|||
|
||||
#elif defined(__mips__)
|
||||
|
||||
#if defined(__misp16) || defined(__mips_micromips)
|
||||
#error "Unsupported encoding"
|
||||
#endif
|
||||
|
||||
int cpu_signal_handler(int host_signum, void *pinfo,
|
||||
void *puc)
|
||||
{
|
||||
siginfo_t *info = pinfo;
|
||||
ucontext_t *uc = puc;
|
||||
greg_t pc = uc->uc_mcontext.pc;
|
||||
int is_write;
|
||||
uintptr_t pc = uc->uc_mcontext.pc;
|
||||
uint32_t insn = *(uint32_t *)pc;
|
||||
int is_write = 0;
|
||||
|
||||
/* Detect all store instructions at program counter. */
|
||||
switch((insn >> 26) & 077) {
|
||||
case 050: /* SB */
|
||||
case 051: /* SH */
|
||||
case 052: /* SWL */
|
||||
case 053: /* SW */
|
||||
case 054: /* SDL */
|
||||
case 055: /* SDR */
|
||||
case 056: /* SWR */
|
||||
case 070: /* SC */
|
||||
case 071: /* SWC1 */
|
||||
case 074: /* SCD */
|
||||
case 075: /* SDC1 */
|
||||
case 077: /* SD */
|
||||
#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
|
||||
case 072: /* SWC2 */
|
||||
case 076: /* SDC2 */
|
||||
#endif
|
||||
is_write = 1;
|
||||
break;
|
||||
case 023: /* COP1X */
|
||||
/* Required in all versions of MIPS64 since
|
||||
MIPS64r1 and subsequent versions of MIPS32r2. */
|
||||
switch (insn & 077) {
|
||||
case 010: /* SWXC1 */
|
||||
case 011: /* SDXC1 */
|
||||
case 015: /* SUXC1 */
|
||||
is_write = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* XXX: compute is_write */
|
||||
is_write = 0;
|
||||
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
||||
}
|
||||
|
||||
|
|
|
@ -20,29 +20,41 @@
|
|||
#ifndef TCG_TCG_GVEC_DESC_H
|
||||
#define TCG_TCG_GVEC_DESC_H
|
||||
|
||||
/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
|
||||
#define SIMD_OPRSZ_SHIFT 0
|
||||
#define SIMD_OPRSZ_BITS 5
|
||||
/*
|
||||
* This configuration allows MAXSZ to represent 2048 bytes, and
|
||||
* OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
|
||||
*
|
||||
* Encode this with:
|
||||
* 0, 1, 3 -> 8, 16, 32
|
||||
* 2 -> maxsz
|
||||
*
|
||||
* This steals the input that would otherwise map to 24 to match maxsz.
|
||||
*/
|
||||
#define SIMD_MAXSZ_SHIFT 0
|
||||
#define SIMD_MAXSZ_BITS 8
|
||||
|
||||
#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
|
||||
#define SIMD_MAXSZ_BITS 5
|
||||
#define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
|
||||
#define SIMD_OPRSZ_BITS 2
|
||||
|
||||
#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
|
||||
#define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
|
||||
#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
|
||||
|
||||
/* Create a descriptor from components. */
|
||||
uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
|
||||
|
||||
/* Extract the operation size from a descriptor. */
|
||||
static inline intptr_t simd_oprsz(uint32_t desc)
|
||||
{
|
||||
return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
|
||||
}
|
||||
|
||||
/* Extract the max vector size from a descriptor. */
|
||||
static inline intptr_t simd_maxsz(uint32_t desc)
|
||||
{
|
||||
return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
|
||||
return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
|
||||
}
|
||||
|
||||
/* Extract the operation size from a descriptor. */
|
||||
static inline intptr_t simd_oprsz(uint32_t desc)
|
||||
{
|
||||
uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
|
||||
intptr_t o = f * 8 + 8;
|
||||
intptr_t m = simd_maxsz(desc);
|
||||
return f == 2 ? m : o;
|
||||
}
|
||||
|
||||
/* Extract the operation-specific data from a descriptor. */
|
||||
|
|
|
@ -976,18 +976,16 @@ int64_t tcg_cpu_exec_time(void);
|
|||
void tcg_dump_info(void);
|
||||
void tcg_dump_op_count(void);
|
||||
|
||||
#define TCG_CT_ALIAS 0x80
|
||||
#define TCG_CT_IALIAS 0x40
|
||||
#define TCG_CT_NEWREG 0x20 /* output requires a new register */
|
||||
#define TCG_CT_REG 0x01
|
||||
#define TCG_CT_CONST 0x02 /* any constant of register size */
|
||||
#define TCG_CT_CONST 1 /* any constant of register size */
|
||||
|
||||
typedef struct TCGArgConstraint {
|
||||
uint16_t ct;
|
||||
uint8_t alias_index;
|
||||
union {
|
||||
TCGRegSet regs;
|
||||
} u;
|
||||
unsigned ct : 16;
|
||||
unsigned alias_index : 4;
|
||||
unsigned sort_index : 4;
|
||||
bool oalias : 1;
|
||||
bool ialias : 1;
|
||||
bool newreg : 1;
|
||||
TCGRegSet regs;
|
||||
} TCGArgConstraint;
|
||||
|
||||
#define TCG_MAX_OP_ARGS 16
|
||||
|
@ -1017,10 +1015,6 @@ typedef struct TCGOpDef {
|
|||
uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
|
||||
uint8_t flags;
|
||||
TCGArgConstraint *args_ct;
|
||||
int *sorted_args;
|
||||
#if defined(CONFIG_DEBUG_TCG)
|
||||
int used;
|
||||
#endif
|
||||
} TCGOpDef;
|
||||
|
||||
extern TCGOpDef tcg_op_defs[];
|
||||
|
|
|
@ -128,23 +128,20 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
{
|
||||
switch (*ct_str++) {
|
||||
case 'r': /* general registers */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs |= 0xffffffffu;
|
||||
ct->regs |= 0xffffffffu;
|
||||
break;
|
||||
case 'w': /* advsimd registers */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs |= 0xffffffff00000000ull;
|
||||
ct->regs |= 0xffffffff00000000ull;
|
||||
break;
|
||||
case 'l': /* qemu_ld / qemu_st address, data_reg */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffffu;
|
||||
ct->regs = 0xffffffffu;
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
/* x0 and x1 will be overwritten when reading the tlb entry,
|
||||
and x2, and x3 for helper args, better to avoid using them. */
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
|
||||
#endif
|
||||
break;
|
||||
case 'A': /* Valid for arithmetic immediate (positive or negative). */
|
||||
|
|
|
@ -139,7 +139,6 @@ typedef enum {
|
|||
#define TCG_TARGET_HAS_shi_vec 1
|
||||
#define TCG_TARGET_HAS_shs_vec 0
|
||||
#define TCG_TARGET_HAS_shv_vec 1
|
||||
#define TCG_TARGET_HAS_cmp_vec 1
|
||||
#define TCG_TARGET_HAS_mul_vec 1
|
||||
#define TCG_TARGET_HAS_sat_vec 1
|
||||
#define TCG_TARGET_HAS_minmax_vec 1
|
||||
|
|
|
@ -253,41 +253,38 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
break;
|
||||
|
||||
case 'r':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffff;
|
||||
ct->regs = 0xffff;
|
||||
break;
|
||||
|
||||
/* qemu_ld address */
|
||||
case 'l':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffff;
|
||||
ct->regs = 0xffff;
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
/* r0-r2,lr will be overwritten when reading the tlb entry,
|
||||
so don't use these. */
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
|
||||
#endif
|
||||
break;
|
||||
|
||||
/* qemu_st address & data */
|
||||
case 's':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffff;
|
||||
ct->regs = 0xffff;
|
||||
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
|
||||
and r0-r1 doing the byte swapping, so don't use these. */
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
/* Avoid clashes with registers being used for helper args */
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
|
||||
#if TARGET_LONG_BITS == 64
|
||||
/* Avoid clashes with registers being used for helper args */
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
|
||||
#endif
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
|
||||
#endif
|
||||
break;
|
||||
|
||||
|
|
|
@ -208,43 +208,34 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
{
|
||||
switch(*ct_str++) {
|
||||
case 'a':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
|
||||
tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
|
||||
break;
|
||||
case 'b':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
|
||||
tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
|
||||
break;
|
||||
case 'c':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
|
||||
tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
|
||||
break;
|
||||
case 'd':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
|
||||
tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
|
||||
break;
|
||||
case 'S':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
|
||||
tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
|
||||
break;
|
||||
case 'D':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
|
||||
tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
|
||||
break;
|
||||
case 'q':
|
||||
/* A register that can be used as a byte operand. */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
|
||||
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
|
||||
break;
|
||||
case 'Q':
|
||||
/* A register with an addressable second byte (e.g. %ah). */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xf;
|
||||
ct->regs = 0xf;
|
||||
break;
|
||||
case 'r':
|
||||
/* A general register. */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs |= ALL_GENERAL_REGS;
|
||||
ct->regs |= ALL_GENERAL_REGS;
|
||||
break;
|
||||
case 'W':
|
||||
/* With TZCNT/LZCNT, we can have operand-size as an input. */
|
||||
|
@ -252,16 +243,14 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
break;
|
||||
case 'x':
|
||||
/* A vector register. */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs |= ALL_VECTOR_REGS;
|
||||
ct->regs |= ALL_VECTOR_REGS;
|
||||
break;
|
||||
|
||||
/* qemu_ld/st address constraint */
|
||||
case 'L':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
|
||||
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
|
||||
break;
|
||||
|
||||
case 'e':
|
||||
|
@ -969,7 +958,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
|
|||
new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
|
||||
} else {
|
||||
if (have_avx2) {
|
||||
tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret);
|
||||
tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
|
||||
} else {
|
||||
tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
|
||||
}
|
||||
|
|
|
@ -189,7 +189,6 @@ extern bool have_avx2;
|
|||
#define TCG_TARGET_HAS_shi_vec 1
|
||||
#define TCG_TARGET_HAS_shs_vec 1
|
||||
#define TCG_TARGET_HAS_shv_vec have_avx2
|
||||
#define TCG_TARGET_HAS_cmp_vec 1
|
||||
#define TCG_TARGET_HAS_mul_vec 1
|
||||
#define TCG_TARGET_HAS_sat_vec 1
|
||||
#define TCG_TARGET_HAS_minmax_vec 1
|
||||
|
|
|
@ -195,29 +195,26 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
{
|
||||
switch(*ct_str++) {
|
||||
case 'r':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
ct->regs = 0xffffffff;
|
||||
break;
|
||||
case 'L': /* qemu_ld input arg constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
|
||||
ct->regs = 0xffffffff;
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
case 'S': /* qemu_st constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
|
||||
ct->regs = 0xffffffff;
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
|
||||
} else {
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
|
|
|
@ -1109,6 +1109,21 @@ void tcg_optimize(TCGContext *s)
|
|||
}
|
||||
goto do_default;
|
||||
|
||||
case INDEX_op_dup2_vec:
|
||||
assert(TCG_TARGET_REG_BITS == 32);
|
||||
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
|
||||
tmp = arg_info(op->args[1])->val;
|
||||
if (tmp == arg_info(op->args[2])->val) {
|
||||
tcg_opt_gen_movi(s, op, op->args[0], tmp);
|
||||
break;
|
||||
}
|
||||
} else if (args_are_copies(op->args[1], op->args[2])) {
|
||||
op->opc = INDEX_op_dup_vec;
|
||||
TCGOP_VECE(op) = MO_32;
|
||||
nb_iargs = 1;
|
||||
}
|
||||
goto do_default;
|
||||
|
||||
CASE_OP_32_64(not):
|
||||
CASE_OP_32_64(neg):
|
||||
CASE_OP_32_64(ext8s):
|
||||
|
|
|
@ -224,34 +224,29 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
{
|
||||
switch (*ct_str++) {
|
||||
case 'A': case 'B': case 'C': case 'D':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
|
||||
tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
|
||||
break;
|
||||
case 'r':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
ct->regs = 0xffffffff;
|
||||
break;
|
||||
case 'v':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff00000000ull;
|
||||
ct->regs = 0xffffffff00000000ull;
|
||||
break;
|
||||
case 'L': /* qemu_ld constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
||||
ct->regs = 0xffffffff;
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
|
||||
#endif
|
||||
break;
|
||||
case 'S': /* qemu_st constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
||||
ct->regs = 0xffffffff;
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
|
||||
#endif
|
||||
break;
|
||||
case 'I':
|
||||
|
|
|
@ -169,7 +169,6 @@ extern bool have_vsx;
|
|||
#define TCG_TARGET_HAS_shi_vec 0
|
||||
#define TCG_TARGET_HAS_shs_vec 0
|
||||
#define TCG_TARGET_HAS_shv_vec 1
|
||||
#define TCG_TARGET_HAS_cmp_vec 1
|
||||
#define TCG_TARGET_HAS_mul_vec 1
|
||||
#define TCG_TARGET_HAS_sat_vec 1
|
||||
#define TCG_TARGET_HAS_minmax_vec 1
|
||||
|
|
|
@ -137,20 +137,18 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
{
|
||||
switch (*ct_str++) {
|
||||
case 'r':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
ct->regs = 0xffffffff;
|
||||
break;
|
||||
case 'L':
|
||||
/* qemu_ld/qemu_st constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
ct->regs = 0xffffffff;
|
||||
/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
|
||||
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
|
||||
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
|
||||
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
|
||||
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
|
||||
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
|
||||
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
|
||||
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
|
||||
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
|
||||
tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
|
||||
#endif
|
||||
break;
|
||||
case 'I':
|
||||
|
|
|
@ -408,25 +408,21 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
{
|
||||
switch (*ct_str++) {
|
||||
case 'r': /* all registers */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffff;
|
||||
ct->regs = 0xffff;
|
||||
break;
|
||||
case 'L': /* qemu_ld/st constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffff;
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
|
||||
ct->regs = 0xffff;
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
|
||||
break;
|
||||
case 'a': /* force R2 for division */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0;
|
||||
tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
|
||||
ct->regs = 0;
|
||||
tcg_regset_set_reg(ct->regs, TCG_REG_R2);
|
||||
break;
|
||||
case 'b': /* force R3 for division */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0;
|
||||
tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
|
||||
ct->regs = 0;
|
||||
tcg_regset_set_reg(ct->regs, TCG_REG_R3);
|
||||
break;
|
||||
case 'A':
|
||||
ct->ct |= TCG_CT_CONST_S33;
|
||||
|
|
|
@ -325,28 +325,23 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
{
|
||||
switch (*ct_str++) {
|
||||
case 'r':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
ct->regs = 0xffffffff;
|
||||
break;
|
||||
case 'R':
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = ALL_64;
|
||||
ct->regs = ALL_64;
|
||||
break;
|
||||
case 'A': /* qemu_ld/st address constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
|
||||
ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
|
||||
reserve_helpers:
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
|
||||
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
|
||||
tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
|
||||
break;
|
||||
case 's': /* qemu_st data 32-bit constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = 0xffffffff;
|
||||
ct->regs = 0xffffffff;
|
||||
goto reserve_helpers;
|
||||
case 'S': /* qemu_st data 64-bit constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = ALL_64;
|
||||
ct->regs = ALL_64;
|
||||
goto reserve_helpers;
|
||||
case 'I':
|
||||
ct->ct |= TCG_CT_CONST_S11;
|
||||
|
|
|
@ -37,11 +37,21 @@ static const TCGOpcode vecop_list_empty[1] = { 0 };
|
|||
of the operand offsets so that we can check them all at once. */
|
||||
static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
|
||||
{
|
||||
uint32_t opr_align = oprsz >= 16 ? 15 : 7;
|
||||
uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
|
||||
tcg_debug_assert(oprsz > 0);
|
||||
tcg_debug_assert(oprsz <= maxsz);
|
||||
tcg_debug_assert((oprsz & opr_align) == 0);
|
||||
uint32_t max_align;
|
||||
|
||||
switch (oprsz) {
|
||||
case 8:
|
||||
case 16:
|
||||
case 32:
|
||||
tcg_debug_assert(oprsz <= maxsz);
|
||||
break;
|
||||
default:
|
||||
tcg_debug_assert(oprsz == maxsz);
|
||||
break;
|
||||
}
|
||||
tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));
|
||||
|
||||
max_align = maxsz >= 16 ? 15 : 7;
|
||||
tcg_debug_assert((maxsz & max_align) == 0);
|
||||
tcg_debug_assert((ofs & max_align) == 0);
|
||||
}
|
||||
|
@ -77,12 +87,21 @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
|
|||
{
|
||||
uint32_t desc = 0;
|
||||
|
||||
assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
|
||||
assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
|
||||
assert(data == sextract32(data, 0, SIMD_DATA_BITS));
|
||||
check_size_align(oprsz, maxsz, 0);
|
||||
tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));
|
||||
|
||||
oprsz = (oprsz / 8) - 1;
|
||||
maxsz = (maxsz / 8) - 1;
|
||||
|
||||
/*
|
||||
* We have just asserted in check_size_align that either
|
||||
* oprsz is {8,16,32} or matches maxsz. Encode the final
|
||||
* case with '2', as that would otherwise map to 24.
|
||||
*/
|
||||
if (oprsz == maxsz) {
|
||||
oprsz = 2;
|
||||
}
|
||||
|
||||
desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
|
||||
desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
|
||||
desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
|
||||
|
|
|
@ -252,10 +252,10 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
|
|||
|
||||
void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
|
||||
{
|
||||
if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
|
||||
do_dupi_vec(r, MO_32, a);
|
||||
} else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
do_dupi_vec(r, MO_64, a);
|
||||
} else if (a == dup_const(MO_32, a)) {
|
||||
do_dupi_vec(r, MO_32, a);
|
||||
} else {
|
||||
TCGv_i64 c = tcg_const_i64(a);
|
||||
tcg_gen_dup_i64_vec(MO_64, r, c);
|
||||
|
@ -280,7 +280,11 @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
|
|||
|
||||
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
|
||||
{
|
||||
do_dupi_vec(r, MO_REG, dup_const(vece, a));
|
||||
if (vece == MO_64) {
|
||||
tcg_gen_dup64i_vec(r, a);
|
||||
} else {
|
||||
do_dupi_vec(r, MO_REG, dup_const(vece, a));
|
||||
}
|
||||
}
|
||||
|
||||
void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
|
||||
|
|
96
tcg/tcg.c
96
tcg/tcg.c
|
@ -944,7 +944,6 @@ void tcg_context_init(TCGContext *s)
|
|||
int op, total_args, n, i;
|
||||
TCGOpDef *def;
|
||||
TCGArgConstraint *args_ct;
|
||||
int *sorted_args;
|
||||
TCGTemp *ts;
|
||||
|
||||
memset(s, 0, sizeof(*s));
|
||||
|
@ -959,15 +958,12 @@ void tcg_context_init(TCGContext *s)
|
|||
total_args += n;
|
||||
}
|
||||
|
||||
args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
|
||||
sorted_args = g_malloc(sizeof(int) * total_args);
|
||||
args_ct = g_new0(TCGArgConstraint, total_args);
|
||||
|
||||
for(op = 0; op < NB_OPS; op++) {
|
||||
def = &tcg_op_defs[op];
|
||||
def->args_ct = args_ct;
|
||||
def->sorted_args = sorted_args;
|
||||
n = def->nb_iargs + def->nb_oargs;
|
||||
sorted_args += n;
|
||||
args_ct += n;
|
||||
}
|
||||
|
||||
|
@ -2198,21 +2194,14 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
|
|||
/* we give more priority to constraints with less registers */
|
||||
static int get_constraint_priority(const TCGOpDef *def, int k)
|
||||
{
|
||||
const TCGArgConstraint *arg_ct;
|
||||
const TCGArgConstraint *arg_ct = &def->args_ct[k];
|
||||
int n;
|
||||
|
||||
int i, n;
|
||||
arg_ct = &def->args_ct[k];
|
||||
if (arg_ct->ct & TCG_CT_ALIAS) {
|
||||
if (arg_ct->oalias) {
|
||||
/* an alias is equivalent to a single register */
|
||||
n = 1;
|
||||
} else {
|
||||
if (!(arg_ct->ct & TCG_CT_REG))
|
||||
return 0;
|
||||
n = 0;
|
||||
for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
|
||||
if (tcg_regset_test_reg(arg_ct->u.regs, i))
|
||||
n++;
|
||||
}
|
||||
n = ctpop64(arg_ct->regs);
|
||||
}
|
||||
return TCG_TARGET_NB_REGS - n + 1;
|
||||
}
|
||||
|
@ -2220,20 +2209,23 @@ static int get_constraint_priority(const TCGOpDef *def, int k)
|
|||
/* sort from highest priority to lowest */
|
||||
static void sort_constraints(TCGOpDef *def, int start, int n)
|
||||
{
|
||||
int i, j, p1, p2, tmp;
|
||||
int i, j;
|
||||
TCGArgConstraint *a = def->args_ct;
|
||||
|
||||
for(i = 0; i < n; i++)
|
||||
def->sorted_args[start + i] = start + i;
|
||||
if (n <= 1)
|
||||
for (i = 0; i < n; i++) {
|
||||
a[start + i].sort_index = start + i;
|
||||
}
|
||||
if (n <= 1) {
|
||||
return;
|
||||
for(i = 0; i < n - 1; i++) {
|
||||
for(j = i + 1; j < n; j++) {
|
||||
p1 = get_constraint_priority(def, def->sorted_args[start + i]);
|
||||
p2 = get_constraint_priority(def, def->sorted_args[start + j]);
|
||||
}
|
||||
for (i = 0; i < n - 1; i++) {
|
||||
for (j = i + 1; j < n; j++) {
|
||||
int p1 = get_constraint_priority(def, a[start + i].sort_index);
|
||||
int p2 = get_constraint_priority(def, a[start + j].sort_index);
|
||||
if (p1 < p2) {
|
||||
tmp = def->sorted_args[start + i];
|
||||
def->sorted_args[start + i] = def->sorted_args[start + j];
|
||||
def->sorted_args[start + j] = tmp;
|
||||
int tmp = a[start + i].sort_index;
|
||||
a[start + i].sort_index = a[start + j].sort_index;
|
||||
a[start + j].sort_index = tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -2268,8 +2260,6 @@ static void process_op_defs(TCGContext *s)
|
|||
/* Incomplete TCGTargetOpDef entry. */
|
||||
tcg_debug_assert(ct_str != NULL);
|
||||
|
||||
def->args_ct[i].u.regs = 0;
|
||||
def->args_ct[i].ct = 0;
|
||||
while (*ct_str != '\0') {
|
||||
switch(*ct_str) {
|
||||
case '0' ... '9':
|
||||
|
@ -2277,19 +2267,19 @@ static void process_op_defs(TCGContext *s)
|
|||
int oarg = *ct_str - '0';
|
||||
tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
|
||||
tcg_debug_assert(oarg < def->nb_oargs);
|
||||
tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
|
||||
/* TCG_CT_ALIAS is for the output arguments.
|
||||
The input is tagged with TCG_CT_IALIAS. */
|
||||
tcg_debug_assert(def->args_ct[oarg].regs != 0);
|
||||
def->args_ct[i] = def->args_ct[oarg];
|
||||
def->args_ct[oarg].ct |= TCG_CT_ALIAS;
|
||||
/* The output sets oalias. */
|
||||
def->args_ct[oarg].oalias = true;
|
||||
def->args_ct[oarg].alias_index = i;
|
||||
def->args_ct[i].ct |= TCG_CT_IALIAS;
|
||||
/* The input sets ialias. */
|
||||
def->args_ct[i].ialias = true;
|
||||
def->args_ct[i].alias_index = oarg;
|
||||
}
|
||||
ct_str++;
|
||||
break;
|
||||
case '&':
|
||||
def->args_ct[i].ct |= TCG_CT_NEWREG;
|
||||
def->args_ct[i].newreg = true;
|
||||
ct_str++;
|
||||
break;
|
||||
case 'i':
|
||||
|
@ -2855,13 +2845,13 @@ static void liveness_pass_1(TCGContext *s)
|
|||
pset = la_temp_pref(ts);
|
||||
set = *pset;
|
||||
|
||||
set &= ct->u.regs;
|
||||
if (ct->ct & TCG_CT_IALIAS) {
|
||||
set &= ct->regs;
|
||||
if (ct->ialias) {
|
||||
set &= op->output_pref[ct->alias_index];
|
||||
}
|
||||
/* If the combination is not possible, restart. */
|
||||
if (set == 0) {
|
||||
set = ct->u.regs;
|
||||
set = ct->regs;
|
||||
}
|
||||
*pset = set;
|
||||
}
|
||||
|
@ -3551,8 +3541,8 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
|
|||
return;
|
||||
}
|
||||
|
||||
dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
|
||||
dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
|
||||
dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
|
||||
dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
|
||||
|
||||
/* Allocate the output register now. */
|
||||
if (ots->val_type != TEMP_VAL_REG) {
|
||||
|
@ -3659,7 +3649,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
|
|||
for (k = 0; k < nb_iargs; k++) {
|
||||
TCGRegSet i_preferred_regs, o_preferred_regs;
|
||||
|
||||
i = def->sorted_args[nb_oargs + k];
|
||||
i = def->args_ct[nb_oargs + k].sort_index;
|
||||
arg = op->args[i];
|
||||
arg_ct = &def->args_ct[i];
|
||||
ts = arg_temp(arg);
|
||||
|
@ -3673,7 +3663,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
|
|||
}
|
||||
|
||||
i_preferred_regs = o_preferred_regs = 0;
|
||||
if (arg_ct->ct & TCG_CT_IALIAS) {
|
||||
if (arg_ct->ialias) {
|
||||
o_preferred_regs = op->output_pref[arg_ct->alias_index];
|
||||
if (ts->fixed_reg) {
|
||||
/* if fixed register, we must allocate a new register
|
||||
|
@ -3695,9 +3685,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
|
|||
int k2, i2;
|
||||
reg = ts->reg;
|
||||
for (k2 = 0 ; k2 < k ; k2++) {
|
||||
i2 = def->sorted_args[nb_oargs + k2];
|
||||
if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
|
||||
reg == new_args[i2]) {
|
||||
i2 = def->args_ct[nb_oargs + k2].sort_index;
|
||||
if (def->args_ct[i2].ialias && reg == new_args[i2]) {
|
||||
goto allocate_in_reg;
|
||||
}
|
||||
}
|
||||
|
@ -3706,10 +3695,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
|
|||
}
|
||||
}
|
||||
|
||||
temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);
|
||||
temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
|
||||
reg = ts->reg;
|
||||
|
||||
if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
|
||||
if (tcg_regset_test_reg(arg_ct->regs, reg)) {
|
||||
/* nothing to do : the constraint is satisfied */
|
||||
} else {
|
||||
allocate_in_reg:
|
||||
|
@ -3717,7 +3706,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
|
|||
and move the temporary register into it */
|
||||
temp_load(s, ts, tcg_target_available_regs[ts->type],
|
||||
i_allocated_regs, 0);
|
||||
reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
|
||||
reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
|
||||
o_preferred_regs, ts->indirect_base);
|
||||
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
|
||||
/*
|
||||
|
@ -3760,7 +3749,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
|
|||
|
||||
/* satisfy the output constraints */
|
||||
for(k = 0; k < nb_oargs; k++) {
|
||||
i = def->sorted_args[k];
|
||||
i = def->args_ct[k].sort_index;
|
||||
arg = op->args[i];
|
||||
arg_ct = &def->args_ct[i];
|
||||
ts = arg_temp(arg);
|
||||
|
@ -3768,15 +3757,14 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
|
|||
/* ENV should not be modified. */
|
||||
tcg_debug_assert(!ts->fixed_reg);
|
||||
|
||||
if ((arg_ct->ct & TCG_CT_ALIAS)
|
||||
&& !const_args[arg_ct->alias_index]) {
|
||||
if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
|
||||
reg = new_args[arg_ct->alias_index];
|
||||
} else if (arg_ct->ct & TCG_CT_NEWREG) {
|
||||
reg = tcg_reg_alloc(s, arg_ct->u.regs,
|
||||
} else if (arg_ct->newreg) {
|
||||
reg = tcg_reg_alloc(s, arg_ct->regs,
|
||||
i_allocated_regs | o_allocated_regs,
|
||||
op->output_pref[k], ts->indirect_base);
|
||||
} else {
|
||||
reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
|
||||
reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
|
||||
op->output_pref[k], ts->indirect_base);
|
||||
}
|
||||
tcg_regset_set_reg(o_allocated_regs, reg);
|
||||
|
|
|
@ -392,8 +392,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
|
|||
case 'r':
|
||||
case 'L': /* qemu_ld constraint */
|
||||
case 'S': /* qemu_st constraint */
|
||||
ct->ct |= TCG_CT_REG;
|
||||
ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
|
||||
ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
|
||||
break;
|
||||
default:
|
||||
return NULL;
|
||||
|
|
Loading…
Reference in New Issue