Remove address masking
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5853 c046a42c-6fe2-441c-8c8c-71466251a162
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0e8f096751
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@ -30,8 +30,7 @@
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/*
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* In addition to Crystal CS4231 there is a DMA controller on Sparc.
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*/
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#define CS_MAXADDR 0x3f
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#define CS_SIZE (CS_MAXADDR + 1)
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#define CS_SIZE 0x40
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#define CS_REGS 16
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#define CS_DREGS 32
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#define CS_MAXDREG (CS_DREGS - 1)
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@ -68,7 +67,7 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
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CSState *s = opaque;
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uint32_t saddr, ret;
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saddr = (addr & CS_MAXADDR) >> 2;
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saddr = addr >> 2;
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switch (saddr) {
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case 1:
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switch (CS_RAP(s)) {
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@ -94,7 +93,7 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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CSState *s = opaque;
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uint32_t saddr;
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saddr = (addr & CS_MAXADDR) >> 2;
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saddr = addr >> 2;
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DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
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switch (saddr) {
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case 1:
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@ -114,7 +114,6 @@
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#define ECC_NREGS 9
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#define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
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#define ECC_ADDR_MASK 0x1f
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#define ECC_DIAG_SIZE 4
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#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
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@ -129,7 +128,7 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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ECCState *s = opaque;
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switch ((addr & ECC_ADDR_MASK) >> 2) {
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switch (addr >> 2) {
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case ECC_MER:
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s->regs[ECC_MER] = (s->regs[ECC_MER] & (ECC_MER_VER | ECC_MER_IMPL)) |
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(val & ~(ECC_MER_VER | ECC_MER_IMPL));
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@ -167,7 +166,7 @@ static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
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ECCState *s = opaque;
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uint32_t ret = 0;
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switch ((addr & ECC_ADDR_MASK) >> 2) {
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switch (addr >> 2) {
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case ECC_MER:
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ret = s->regs[ECC_MER];
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DPRINTF("Read memory enable %08x\n", ret);
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@ -225,15 +224,16 @@ static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
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{
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ECCState *s = opaque;
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DPRINTF("Write diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), val);
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DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
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s->diag[addr & ECC_DIAG_MASK] = val;
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}
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static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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ECCState *s = opaque;
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uint32_t ret = s->diag[addr & ECC_DIAG_MASK];
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DPRINTF("Read diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), ret);
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uint32_t ret = s->diag[(int)addr];
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DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
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return ret;
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}
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4
hw/esp.c
4
hw/esp.c
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@ -425,7 +425,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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ESPState *s = opaque;
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uint32_t saddr;
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saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
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saddr = addr >> s->it_shift;
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DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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switch (saddr) {
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case ESP_FIFO:
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@ -461,7 +461,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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ESPState *s = opaque;
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uint32_t saddr;
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saddr = (addr >> s->it_shift) & (ESP_REGS - 1);
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saddr = addr >> s->it_shift;
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DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
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val);
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switch (saddr) {
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30
hw/fdc.c
30
hw/fdc.c
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@ -513,7 +513,7 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg)
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fdctrl_t *fdctrl = opaque;
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uint32_t retval;
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switch (reg & 0x07) {
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switch (reg) {
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case FD_REG_SRA:
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retval = fdctrl_read_statusA(fdctrl);
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break;
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@ -550,7 +550,7 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
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FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
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switch (reg & 0x07) {
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switch (reg) {
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case FD_REG_DOR:
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fdctrl_write_dor(fdctrl, value);
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break;
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@ -568,6 +568,16 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
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}
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}
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static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
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{
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return fdctrl_read(opaque, reg & 7);
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}
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static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
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{
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fdctrl_write(opaque, reg & 7, value);
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}
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static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
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{
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return fdctrl_read(opaque, (uint32_t)reg);
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@ -1896,14 +1906,14 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
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fdctrl);
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cpu_register_physical_memory(io_base, 0x08, io_mem);
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} else {
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register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
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fdctrl);
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register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
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fdctrl);
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register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
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fdctrl);
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register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
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fdctrl);
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register_ioport_read((uint32_t)io_base + 0x01, 5, 1,
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&fdctrl_read_port, fdctrl);
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register_ioport_read((uint32_t)io_base + 0x07, 1, 1,
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&fdctrl_read_port, fdctrl);
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register_ioport_write((uint32_t)io_base + 0x01, 5, 1,
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&fdctrl_write_port, fdctrl);
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register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
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&fdctrl_write_port, fdctrl);
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}
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return fdctrl;
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@ -2060,14 +2060,14 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
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printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr,
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val & 0xffff);
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#endif
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pcnet_ioport_writew(opaque, addr & 7, val & 0xffff);
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pcnet_ioport_writew(opaque, addr, val & 0xffff);
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}
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static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = pcnet_ioport_readw(opaque, addr & 7);
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val = pcnet_ioport_readw(opaque, addr);
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#ifdef PCNET_DEBUG_IO
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printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
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val & 0xffff);
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5
hw/sbi.c
5
hw/sbi.c
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@ -46,7 +46,6 @@ typedef struct SBIState {
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} SBIState;
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#define SBI_SIZE (SBI_NREGS * 4)
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#define SBI_MASK (SBI_SIZE - 1)
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static void sbi_check_interrupts(void *opaque)
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{
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@ -65,7 +64,7 @@ static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
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SBIState *s = opaque;
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uint32_t saddr, ret;
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saddr = (addr & SBI_MASK) >> 2;
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saddr = addr >> 2;
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switch (saddr) {
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default:
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ret = s->regs[saddr];
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@ -81,7 +80,7 @@ static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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SBIState *s = opaque;
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uint32_t saddr;
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saddr = (addr & SBI_MASK) >> 2;
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saddr = addr >> 2;
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DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
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switch (saddr) {
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default:
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@ -108,8 +108,7 @@ struct SerialState {
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struct ChannelState chn[2];
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};
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#define SERIAL_MAXADDR 7
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#define SERIAL_SIZE (SERIAL_MAXADDR + 1)
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#define SERIAL_SIZE 8
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#define SERIAL_CTRL 0
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#define SERIAL_DATA 1
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@ -477,7 +476,7 @@ static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr,
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val &= 0xff;
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saddr = (addr & 3) >> 1;
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channel = (addr & SERIAL_MAXADDR) >> 2;
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channel = addr >> 2;
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s = &serial->chn[channel];
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switch (saddr) {
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case SERIAL_CTRL:
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@ -574,7 +573,7 @@ static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
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int channel;
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saddr = (addr & 3) >> 1;
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channel = (addr & SERIAL_MAXADDR) >> 2;
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channel = addr >> 2;
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s = &serial->chn[channel];
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switch (saddr) {
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case SERIAL_CTRL:
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@ -66,7 +66,6 @@ typedef struct SLAVIO_TIMERState {
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uint32_t slave_mode;
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} SLAVIO_TIMERState;
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#define TIMER_MAXADDR 0x1f
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#define SYS_TIMER_SIZE 0x14
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#define CPU_TIMER_SIZE 0x10
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@ -132,7 +131,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
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SLAVIO_TIMERState *s = opaque;
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uint32_t saddr, ret;
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saddr = (addr & TIMER_MAXADDR) >> 2;
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saddr = addr >> 2;
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switch (saddr) {
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case TIMER_LIMIT:
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// read limit (system counter mode) or read most signifying
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@ -185,7 +184,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t saddr;
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DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
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saddr = (addr & TIMER_MAXADDR) >> 2;
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saddr = addr >> 2;
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switch (saddr) {
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case TIMER_LIMIT:
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if (slavio_timer_is_user(s)) {
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@ -45,7 +45,6 @@ do { printf("DMA: " fmt , ##args); } while (0)
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#define DMA_REGS 4
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#define DMA_SIZE (4 * sizeof(uint32_t))
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#define DMA_MAXADDR (DMA_SIZE - 1)
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#define DMA_VER 0xa0000000
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#define DMA_INTR 1
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@ -157,7 +156,7 @@ static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
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DMAState *s = opaque;
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uint32_t saddr;
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saddr = (addr & DMA_MAXADDR) >> 2;
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saddr = addr >> 2;
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DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
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s->dmaregs[saddr]);
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@ -169,7 +168,7 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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DMAState *s = opaque;
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uint32_t saddr;
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saddr = (addr & DMA_MAXADDR) >> 2;
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saddr = addr >> 2;
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DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
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s->dmaregs[saddr], val);
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switch (saddr) {
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@ -52,8 +52,7 @@ typedef struct Sun4c_INTCTLState {
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uint8_t pending;
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} Sun4c_INTCTLState;
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#define INTCTL_MAXADDR 0
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#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
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#define INTCTL_SIZE 1
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static void sun4c_check_interrupts(void *opaque);
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6
hw/tcx.c
6
hw/tcx.c
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@ -437,15 +437,13 @@ static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
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static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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TCXState *s = opaque;
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uint32_t saddr;
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saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
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switch (saddr) {
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switch (addr) {
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case 0:
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s->dac_index = val >> 24;
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s->dac_state = 0;
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break;
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case 1:
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case 4:
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switch (s->dac_state) {
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case 0:
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s->r[s->dac_index] = val >> 24;
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