tests/qtests: Add npcm7xx emc model test
Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-4-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Doug Evans
Peter Maydell
parent
7758643650
commit
e6646167cc
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@ -141,7 +141,8 @@ qtests_npcm7xx = \
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'npcm7xx_rng-test',
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'npcm7xx_smbus-test',
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'npcm7xx_timer-test',
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'npcm7xx_watchdog_timer-test']
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'npcm7xx_watchdog_timer-test'] + \
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(slirp.found() ? ['npcm7xx_emc-test'] : [])
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qtests_arm = \
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(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
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(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
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@ -0,0 +1,862 @@
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/*
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* QTests for Nuvoton NPCM7xx EMC Modules.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "libqos/libqos.h"
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#include "qapi/qmp/qdict.h"
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#include "qapi/qmp/qnum.h"
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#include "qemu/bitops.h"
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#include "qemu/iov.h"
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/* Name of the emc device. */
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#define TYPE_NPCM7XX_EMC "npcm7xx-emc"
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/* Timeout for various operations, in seconds. */
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#define TIMEOUT_SECONDS 10
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/* Address in memory of the descriptor. */
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#define DESC_ADDR (1 << 20) /* 1 MiB */
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/* Address in memory of the data packet. */
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#define DATA_ADDR (DESC_ADDR + 4096)
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#define CRC_LENGTH 4
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#define NUM_TX_DESCRIPTORS 3
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#define NUM_RX_DESCRIPTORS 2
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/* Size of tx,rx test buffers. */
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#define TX_DATA_LEN 64
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#define RX_DATA_LEN 64
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#define TX_STEP_COUNT 10000
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#define RX_STEP_COUNT 10000
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/* 32-bit register indices. */
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typedef enum NPCM7xxPWMRegister {
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/* Control registers. */
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REG_CAMCMR,
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REG_CAMEN,
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/* There are 16 CAMn[ML] registers. */
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REG_CAMM_BASE,
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REG_CAML_BASE,
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REG_TXDLSA = 0x22,
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REG_RXDLSA,
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REG_MCMDR,
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REG_MIID,
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REG_MIIDA,
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REG_FFTCR,
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REG_TSDR,
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REG_RSDR,
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REG_DMARFC,
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REG_MIEN,
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/* Status registers. */
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REG_MISTA,
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REG_MGSTA,
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REG_MPCNT,
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REG_MRPC,
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REG_MRPCC,
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REG_MREPC,
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REG_DMARFS,
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REG_CTXDSA,
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REG_CTXBSA,
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REG_CRXDSA,
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REG_CRXBSA,
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NPCM7XX_NUM_EMC_REGS,
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} NPCM7xxPWMRegister;
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enum { NUM_CAMML_REGS = 16 };
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/* REG_CAMCMR fields */
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/* Enable CAM Compare */
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#define REG_CAMCMR_ECMP (1 << 4)
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/* Accept Unicast Packet */
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#define REG_CAMCMR_AUP (1 << 0)
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/* REG_MCMDR fields */
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/* Software Reset */
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#define REG_MCMDR_SWR (1 << 24)
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/* Frame Transmission On */
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#define REG_MCMDR_TXON (1 << 8)
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/* Accept Long Packet */
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#define REG_MCMDR_ALP (1 << 1)
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/* Frame Reception On */
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#define REG_MCMDR_RXON (1 << 0)
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/* REG_MIEN fields */
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/* Enable Transmit Completion Interrupt */
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#define REG_MIEN_ENTXCP (1 << 18)
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/* Enable Transmit Interrupt */
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#define REG_MIEN_ENTXINTR (1 << 16)
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/* Enable Receive Good Interrupt */
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#define REG_MIEN_ENRXGD (1 << 4)
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/* ENable Receive Interrupt */
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#define REG_MIEN_ENRXINTR (1 << 0)
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/* REG_MISTA fields */
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/* Transmit Bus Error Interrupt */
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#define REG_MISTA_TXBERR (1 << 24)
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/* Transmit Descriptor Unavailable Interrupt */
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#define REG_MISTA_TDU (1 << 23)
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/* Transmit Completion Interrupt */
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#define REG_MISTA_TXCP (1 << 18)
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/* Transmit Interrupt */
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#define REG_MISTA_TXINTR (1 << 16)
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/* Receive Bus Error Interrupt */
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#define REG_MISTA_RXBERR (1 << 11)
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/* Receive Descriptor Unavailable Interrupt */
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#define REG_MISTA_RDU (1 << 10)
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/* DMA Early Notification Interrupt */
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#define REG_MISTA_DENI (1 << 9)
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/* Maximum Frame Length Interrupt */
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#define REG_MISTA_DFOI (1 << 8)
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/* Receive Good Interrupt */
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#define REG_MISTA_RXGD (1 << 4)
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/* Packet Too Long Interrupt */
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#define REG_MISTA_PTLE (1 << 3)
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/* Receive Interrupt */
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#define REG_MISTA_RXINTR (1 << 0)
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typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc;
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typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc;
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struct NPCM7xxEMCTxDesc {
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uint32_t flags;
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uint32_t txbsa;
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uint32_t status_and_length;
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uint32_t ntxdsa;
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};
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struct NPCM7xxEMCRxDesc {
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uint32_t status_and_length;
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uint32_t rxbsa;
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uint32_t reserved;
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uint32_t nrxdsa;
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};
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/* NPCM7xxEMCTxDesc.flags values */
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/* Owner: 0 = cpu, 1 = emc */
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#define TX_DESC_FLAG_OWNER_MASK (1 << 31)
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/* Transmit interrupt enable */
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#define TX_DESC_FLAG_INTEN (1 << 2)
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/* NPCM7xxEMCTxDesc.status_and_length values */
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/* Transmission complete */
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#define TX_DESC_STATUS_TXCP (1 << 19)
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/* Transmit interrupt */
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#define TX_DESC_STATUS_TXINTR (1 << 16)
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/* NPCM7xxEMCRxDesc.status_and_length values */
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/* Owner: 0b00 = cpu, 0b10 = emc */
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#define RX_DESC_STATUS_OWNER_SHIFT 30
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#define RX_DESC_STATUS_OWNER_MASK 0xc0000000
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/* Frame Reception Complete */
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#define RX_DESC_STATUS_RXGD (1 << 20)
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/* Packet too long */
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#define RX_DESC_STATUS_PTLE (1 << 19)
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/* Receive Interrupt */
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#define RX_DESC_STATUS_RXINTR (1 << 16)
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#define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff)
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typedef struct EMCModule {
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int rx_irq;
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int tx_irq;
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uint64_t base_addr;
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} EMCModule;
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typedef struct TestData {
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const EMCModule *module;
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} TestData;
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static const EMCModule emc_module_list[] = {
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{
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.rx_irq = 15,
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.tx_irq = 16,
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.base_addr = 0xf0825000
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},
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{
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.rx_irq = 114,
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.tx_irq = 115,
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.base_addr = 0xf0826000
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}
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};
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/* Returns the index of the EMC module. */
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static int emc_module_index(const EMCModule *mod)
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{
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ptrdiff_t diff = mod - emc_module_list;
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g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list));
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return diff;
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}
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static void packet_test_clear(void *sockets)
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{
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int *test_sockets = sockets;
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close(test_sockets[0]);
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g_free(test_sockets);
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}
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static int *packet_test_init(int module_num, GString *cmd_line)
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{
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int *test_sockets = g_new(int, 2);
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int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
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g_assert_cmpint(ret, != , -1);
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/*
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* KISS and use -nic. We specify two nics (both emc{0,1}) because there's
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* currently no way to specify only emc1: The driver implicitly relies on
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* emc[i] == nd_table[i].
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*/
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if (module_num == 0) {
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g_string_append_printf(cmd_line,
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" -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " "
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" -nic user,model=" TYPE_NPCM7XX_EMC " ",
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test_sockets[1]);
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} else {
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g_string_append_printf(cmd_line,
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" -nic user,model=" TYPE_NPCM7XX_EMC " "
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" -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " ",
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test_sockets[1]);
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}
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g_test_queue_destroy(packet_test_clear, test_sockets);
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return test_sockets;
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}
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static uint32_t emc_read(QTestState *qts, const EMCModule *mod,
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NPCM7xxPWMRegister regno)
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{
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return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t));
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}
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static void emc_write(QTestState *qts, const EMCModule *mod,
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NPCM7xxPWMRegister regno, uint32_t value)
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{
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qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value);
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}
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static void emc_read_tx_desc(QTestState *qts, uint32_t addr,
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NPCM7xxEMCTxDesc *desc)
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{
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qtest_memread(qts, addr, desc, sizeof(*desc));
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desc->flags = le32_to_cpu(desc->flags);
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desc->txbsa = le32_to_cpu(desc->txbsa);
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desc->status_and_length = le32_to_cpu(desc->status_and_length);
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desc->ntxdsa = le32_to_cpu(desc->ntxdsa);
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}
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static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc,
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uint32_t addr)
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{
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NPCM7xxEMCTxDesc le_desc;
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le_desc.flags = cpu_to_le32(desc->flags);
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le_desc.txbsa = cpu_to_le32(desc->txbsa);
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le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
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le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa);
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qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
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}
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static void emc_read_rx_desc(QTestState *qts, uint32_t addr,
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NPCM7xxEMCRxDesc *desc)
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{
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qtest_memread(qts, addr, desc, sizeof(*desc));
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desc->status_and_length = le32_to_cpu(desc->status_and_length);
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desc->rxbsa = le32_to_cpu(desc->rxbsa);
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desc->reserved = le32_to_cpu(desc->reserved);
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desc->nrxdsa = le32_to_cpu(desc->nrxdsa);
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}
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static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc,
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uint32_t addr)
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{
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NPCM7xxEMCRxDesc le_desc;
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le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
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le_desc.rxbsa = cpu_to_le32(desc->rxbsa);
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le_desc.reserved = cpu_to_le32(desc->reserved);
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le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa);
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qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
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}
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/*
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* Reset the EMC module.
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* The module must be reset before, e.g., TXDLSA,RXDLSA are changed.
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*/
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static bool emc_soft_reset(QTestState *qts, const EMCModule *mod)
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{
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uint32_t val;
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uint64_t end_time;
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emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR);
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/*
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* Wait for device to reset as the linux driver does.
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* During reset the AHB reads 0 for all registers. So first wait for
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* something that resets to non-zero, and then wait for SWR becoming 0.
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*/
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end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
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do {
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qtest_clock_step(qts, 100);
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val = emc_read(qts, mod, REG_FFTCR);
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} while (val == 0 && g_get_monotonic_time() < end_time);
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if (val != 0) {
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do {
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qtest_clock_step(qts, 100);
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val = emc_read(qts, mod, REG_MCMDR);
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if ((val & REG_MCMDR_SWR) == 0) {
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/*
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* N.B. The CAMs have been reset here, so macaddr matching of
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* incoming packets will not work.
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*/
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return true;
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}
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} while (g_get_monotonic_time() < end_time);
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}
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g_message("%s: Timeout expired", __func__);
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return false;
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}
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/* Check emc registers are reset to default value. */
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static void test_init(gconstpointer test_data)
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{
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const TestData *td = test_data;
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const EMCModule *mod = td->module;
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QTestState *qts = qtest_init("-machine quanta-gsj");
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int i;
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#define CHECK_REG(regno, value) \
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do { \
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g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \
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} while (0)
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CHECK_REG(REG_CAMCMR, 0);
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CHECK_REG(REG_CAMEN, 0);
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CHECK_REG(REG_TXDLSA, 0xfffffffc);
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CHECK_REG(REG_RXDLSA, 0xfffffffc);
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CHECK_REG(REG_MCMDR, 0);
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CHECK_REG(REG_MIID, 0);
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CHECK_REG(REG_MIIDA, 0x00900000);
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CHECK_REG(REG_FFTCR, 0x0101);
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CHECK_REG(REG_DMARFC, 0x0800);
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CHECK_REG(REG_MIEN, 0);
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CHECK_REG(REG_MISTA, 0);
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CHECK_REG(REG_MGSTA, 0);
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CHECK_REG(REG_MPCNT, 0x7fff);
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CHECK_REG(REG_MRPC, 0);
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CHECK_REG(REG_MRPCC, 0);
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CHECK_REG(REG_MREPC, 0);
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CHECK_REG(REG_DMARFS, 0);
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CHECK_REG(REG_CTXDSA, 0);
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CHECK_REG(REG_CTXBSA, 0);
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CHECK_REG(REG_CRXDSA, 0);
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CHECK_REG(REG_CRXBSA, 0);
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#undef CHECK_REG
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for (i = 0; i < NUM_CAMML_REGS; ++i) {
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g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==,
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0);
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g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==,
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0);
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}
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qtest_quit(qts);
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}
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static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step,
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bool is_tx)
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{
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uint64_t end_time =
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g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
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do {
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if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) {
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return true;
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}
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qtest_clock_step(qts, step);
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} while (g_get_monotonic_time() < end_time);
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g_message("%s: Timeout expired", __func__);
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return false;
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}
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static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step,
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uint32_t flag)
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{
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uint64_t end_time =
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g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
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do {
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uint32_t mista = emc_read(qts, mod, REG_MISTA);
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if (mista & flag) {
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return true;
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}
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qtest_clock_step(qts, step);
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} while (g_get_monotonic_time() < end_time);
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g_message("%s: Timeout expired", __func__);
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return false;
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}
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static bool wait_socket_readable(int fd)
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{
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fd_set read_fds;
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struct timeval tv;
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int rv;
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FD_ZERO(&read_fds);
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FD_SET(fd, &read_fds);
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tv.tv_sec = TIMEOUT_SECONDS;
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tv.tv_usec = 0;
|
||||
rv = select(fd + 1, &read_fds, NULL, NULL, &tv);
|
||||
if (rv == -1) {
|
||||
perror("select");
|
||||
} else if (rv == 0) {
|
||||
g_message("%s: Timeout expired", __func__);
|
||||
}
|
||||
return rv == 1;
|
||||
}
|
||||
|
||||
/* Initialize *desc (in host endian format). */
|
||||
static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count,
|
||||
uint32_t desc_addr)
|
||||
{
|
||||
g_assert(count >= 2);
|
||||
memset(&desc[0], 0, sizeof(*desc) * count);
|
||||
/* Leave the last one alone, owned by the cpu -> stops transmission. */
|
||||
for (size_t i = 0; i < count - 1; ++i) {
|
||||
desc[i].flags =
|
||||
(TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */
|
||||
TX_DESC_FLAG_INTEN |
|
||||
0 | /* crc append = 0 */
|
||||
0 /* padding enable = 0 */);
|
||||
desc[i].status_and_length =
|
||||
(0 | /* collision count = 0 */
|
||||
0 | /* SQE = 0 */
|
||||
0 | /* PAU = 0 */
|
||||
0 | /* TXHA = 0 */
|
||||
0 | /* LC = 0 */
|
||||
0 | /* TXABT = 0 */
|
||||
0 | /* NCS = 0 */
|
||||
0 | /* EXDEF = 0 */
|
||||
0 | /* TXCP = 0 */
|
||||
0 | /* DEF = 0 */
|
||||
0 | /* TXINTR = 0 */
|
||||
0 /* length filled in later */);
|
||||
desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc);
|
||||
}
|
||||
}
|
||||
|
||||
static void enable_tx(QTestState *qts, const EMCModule *mod,
|
||||
const NPCM7xxEMCTxDesc *desc, size_t count,
|
||||
uint32_t desc_addr, uint32_t mien_flags)
|
||||
{
|
||||
/* Write the descriptors to guest memory. */
|
||||
for (size_t i = 0; i < count; ++i) {
|
||||
emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
|
||||
}
|
||||
|
||||
/* Trigger sending the packet. */
|
||||
/* The module must be reset before changing TXDLSA. */
|
||||
g_assert(emc_soft_reset(qts, mod));
|
||||
emc_write(qts, mod, REG_TXDLSA, desc_addr);
|
||||
emc_write(qts, mod, REG_CTXDSA, ~0);
|
||||
emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags);
|
||||
{
|
||||
uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
|
||||
mcmdr |= REG_MCMDR_TXON;
|
||||
emc_write(qts, mod, REG_MCMDR, mcmdr);
|
||||
}
|
||||
|
||||
/* Prod the device to send the packet. */
|
||||
emc_write(qts, mod, REG_TSDR, 1);
|
||||
}
|
||||
|
||||
static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd,
|
||||
bool with_irq, uint32_t desc_addr,
|
||||
uint32_t next_desc_addr,
|
||||
const char *test_data, int test_size)
|
||||
{
|
||||
NPCM7xxEMCTxDesc result_desc;
|
||||
uint32_t expected_mask, expected_value, recv_len;
|
||||
int ret;
|
||||
char buffer[TX_DATA_LEN];
|
||||
|
||||
g_assert(wait_socket_readable(fd));
|
||||
|
||||
/* Read the descriptor back. */
|
||||
emc_read_tx_desc(qts, desc_addr, &result_desc);
|
||||
/* Descriptor should be owned by cpu now. */
|
||||
g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0);
|
||||
/* Test the status bits, ignoring the length field. */
|
||||
expected_mask = 0xffff << 16;
|
||||
expected_value = TX_DESC_STATUS_TXCP;
|
||||
if (with_irq) {
|
||||
expected_value |= TX_DESC_STATUS_TXINTR;
|
||||
}
|
||||
g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
|
||||
expected_value);
|
||||
|
||||
/* Check data sent to the backend. */
|
||||
recv_len = ~0;
|
||||
ret = qemu_recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT);
|
||||
g_assert_cmpint(ret, == , sizeof(recv_len));
|
||||
|
||||
g_assert(wait_socket_readable(fd));
|
||||
memset(buffer, 0xff, sizeof(buffer));
|
||||
ret = qemu_recv(fd, buffer, test_size, MSG_DONTWAIT);
|
||||
g_assert_cmpmem(buffer, ret, test_data, test_size);
|
||||
}
|
||||
|
||||
static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd,
|
||||
bool with_irq)
|
||||
{
|
||||
NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS];
|
||||
uint32_t desc_addr = DESC_ADDR;
|
||||
static const char test1_data[] = "TEST1";
|
||||
static const char test2_data[] = "Testing 1 2 3 ...";
|
||||
uint32_t data1_addr = DATA_ADDR;
|
||||
uint32_t data2_addr = data1_addr + sizeof(test1_data);
|
||||
bool got_tdu;
|
||||
uint32_t end_desc_addr;
|
||||
|
||||
/* Prepare test data buffer. */
|
||||
qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data));
|
||||
qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data));
|
||||
|
||||
init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr);
|
||||
desc[0].txbsa = data1_addr;
|
||||
desc[0].status_and_length |= sizeof(test1_data);
|
||||
desc[1].txbsa = data2_addr;
|
||||
desc[1].status_and_length |= sizeof(test2_data);
|
||||
|
||||
enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr,
|
||||
with_irq ? REG_MIEN_ENTXINTR : 0);
|
||||
|
||||
/*
|
||||
* It's problematic to observe the interrupt for each packet.
|
||||
* Instead just wait until all the packets go out.
|
||||
*/
|
||||
got_tdu = false;
|
||||
while (!got_tdu) {
|
||||
if (with_irq) {
|
||||
g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT,
|
||||
/*is_tx=*/true));
|
||||
} else {
|
||||
g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT,
|
||||
REG_MISTA_TXINTR));
|
||||
}
|
||||
got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU);
|
||||
/* If we don't have TDU yet, reset the interrupt. */
|
||||
if (!got_tdu) {
|
||||
emc_write(qts, mod, REG_MISTA,
|
||||
emc_read(qts, mod, REG_MISTA) & 0xffff0000);
|
||||
}
|
||||
}
|
||||
|
||||
end_desc_addr = desc_addr + 2 * sizeof(desc[0]);
|
||||
g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr);
|
||||
g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==,
|
||||
REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU);
|
||||
|
||||
emc_send_verify1(qts, mod, fd, with_irq,
|
||||
desc_addr, end_desc_addr,
|
||||
test1_data, sizeof(test1_data));
|
||||
emc_send_verify1(qts, mod, fd, with_irq,
|
||||
desc_addr + sizeof(desc[0]), end_desc_addr,
|
||||
test2_data, sizeof(test2_data));
|
||||
}
|
||||
|
||||
/* Initialize *desc (in host endian format). */
|
||||
static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count,
|
||||
uint32_t desc_addr, uint32_t data_addr)
|
||||
{
|
||||
g_assert_true(count >= 2);
|
||||
memset(desc, 0, sizeof(*desc) * count);
|
||||
desc[0].rxbsa = data_addr;
|
||||
desc[0].status_and_length =
|
||||
(0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */
|
||||
0 | /* RP = 0 */
|
||||
0 | /* ALIE = 0 */
|
||||
0 | /* RXGD = 0 */
|
||||
0 | /* PTLE = 0 */
|
||||
0 | /* CRCE = 0 */
|
||||
0 | /* RXINTR = 0 */
|
||||
0 /* length (filled in later) */);
|
||||
/* Leave the last one alone, owned by the cpu -> stops transmission. */
|
||||
desc[0].nrxdsa = desc_addr + sizeof(*desc);
|
||||
}
|
||||
|
||||
static void enable_rx(QTestState *qts, const EMCModule *mod,
|
||||
const NPCM7xxEMCRxDesc *desc, size_t count,
|
||||
uint32_t desc_addr, uint32_t mien_flags,
|
||||
uint32_t mcmdr_flags)
|
||||
{
|
||||
/*
|
||||
* Write the descriptor to guest memory.
|
||||
* FWIW, IWBN if the docs said the buffer needs to be at least DMARFC
|
||||
* bytes.
|
||||
*/
|
||||
for (size_t i = 0; i < count; ++i) {
|
||||
emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
|
||||
}
|
||||
|
||||
/* Trigger receiving the packet. */
|
||||
/* The module must be reset before changing RXDLSA. */
|
||||
g_assert(emc_soft_reset(qts, mod));
|
||||
emc_write(qts, mod, REG_RXDLSA, desc_addr);
|
||||
emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags);
|
||||
|
||||
/*
|
||||
* We don't know what the device's macaddr is, so just accept all
|
||||
* unicast packets (AUP).
|
||||
*/
|
||||
emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP);
|
||||
emc_write(qts, mod, REG_CAMEN, 1 << 0);
|
||||
{
|
||||
uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
|
||||
mcmdr |= REG_MCMDR_RXON | mcmdr_flags;
|
||||
emc_write(qts, mod, REG_MCMDR, mcmdr);
|
||||
}
|
||||
|
||||
/* Prod the device to accept a packet. */
|
||||
emc_write(qts, mod, REG_RSDR, 1);
|
||||
}
|
||||
|
||||
static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd,
|
||||
bool with_irq)
|
||||
{
|
||||
NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
|
||||
uint32_t desc_addr = DESC_ADDR;
|
||||
uint32_t data_addr = DATA_ADDR;
|
||||
int ret;
|
||||
uint32_t expected_mask, expected_value;
|
||||
NPCM7xxEMCRxDesc result_desc;
|
||||
|
||||
/* Prepare test data buffer. */
|
||||
const char test[RX_DATA_LEN] = "TEST";
|
||||
int len = htonl(sizeof(test));
|
||||
const struct iovec iov[] = {
|
||||
{
|
||||
.iov_base = &len,
|
||||
.iov_len = sizeof(len),
|
||||
},{
|
||||
.iov_base = (char *) test,
|
||||
.iov_len = sizeof(test),
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Reset the device BEFORE sending a test packet, otherwise the packet
|
||||
* may get swallowed by an active device of an earlier test.
|
||||
*/
|
||||
init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
|
||||
enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
|
||||
with_irq ? REG_MIEN_ENRXINTR : 0, 0);
|
||||
|
||||
/* Send test packet to device's socket. */
|
||||
ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test));
|
||||
g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
|
||||
|
||||
/* Wait for RX interrupt. */
|
||||
if (with_irq) {
|
||||
g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
|
||||
} else {
|
||||
g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD));
|
||||
}
|
||||
|
||||
g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==,
|
||||
desc_addr + sizeof(desc[0]));
|
||||
|
||||
expected_mask = 0xffff;
|
||||
expected_value = (REG_MISTA_DENI |
|
||||
REG_MISTA_RXGD |
|
||||
REG_MISTA_RXINTR);
|
||||
g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask),
|
||||
==, expected_value);
|
||||
|
||||
/* Read the descriptor back. */
|
||||
emc_read_rx_desc(qts, desc_addr, &result_desc);
|
||||
/* Descriptor should be owned by cpu now. */
|
||||
g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
|
||||
/* Test the status bits, ignoring the length field. */
|
||||
expected_mask = 0xffff << 16;
|
||||
expected_value = RX_DESC_STATUS_RXGD;
|
||||
if (with_irq) {
|
||||
expected_value |= RX_DESC_STATUS_RXINTR;
|
||||
}
|
||||
g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
|
||||
expected_value);
|
||||
g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
|
||||
RX_DATA_LEN + CRC_LENGTH);
|
||||
|
||||
{
|
||||
char buffer[RX_DATA_LEN];
|
||||
qtest_memread(qts, data_addr, buffer, sizeof(buffer));
|
||||
g_assert_cmpstr(buffer, == , "TEST");
|
||||
}
|
||||
}
|
||||
|
||||
static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd)
|
||||
{
|
||||
NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
|
||||
uint32_t desc_addr = DESC_ADDR;
|
||||
uint32_t data_addr = DATA_ADDR;
|
||||
int ret;
|
||||
NPCM7xxEMCRxDesc result_desc;
|
||||
uint32_t expected_mask, expected_value;
|
||||
|
||||
/* Prepare test data buffer. */
|
||||
#define PTLE_DATA_LEN 1600
|
||||
char test_data[PTLE_DATA_LEN];
|
||||
int len = htonl(sizeof(test_data));
|
||||
const struct iovec iov[] = {
|
||||
{
|
||||
.iov_base = &len,
|
||||
.iov_len = sizeof(len),
|
||||
},{
|
||||
.iov_base = (char *) test_data,
|
||||
.iov_len = sizeof(test_data),
|
||||
},
|
||||
};
|
||||
memset(test_data, 42, sizeof(test_data));
|
||||
|
||||
/*
|
||||
* Reset the device BEFORE sending a test packet, otherwise the packet
|
||||
* may get swallowed by an active device of an earlier test.
|
||||
*/
|
||||
init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
|
||||
enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
|
||||
REG_MIEN_ENRXINTR, REG_MCMDR_ALP);
|
||||
|
||||
/* Send test packet to device's socket. */
|
||||
ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data));
|
||||
g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len));
|
||||
|
||||
/* Wait for RX interrupt. */
|
||||
g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
|
||||
|
||||
/* Read the descriptor back. */
|
||||
emc_read_rx_desc(qts, desc_addr, &result_desc);
|
||||
/* Descriptor should be owned by cpu now. */
|
||||
g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
|
||||
/* Test the status bits, ignoring the length field. */
|
||||
expected_mask = 0xffff << 16;
|
||||
expected_value = (RX_DESC_STATUS_RXGD |
|
||||
RX_DESC_STATUS_PTLE |
|
||||
RX_DESC_STATUS_RXINTR);
|
||||
g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
|
||||
expected_value);
|
||||
g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
|
||||
PTLE_DATA_LEN + CRC_LENGTH);
|
||||
|
||||
{
|
||||
char buffer[PTLE_DATA_LEN];
|
||||
qtest_memread(qts, data_addr, buffer, sizeof(buffer));
|
||||
g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void test_tx(gconstpointer test_data)
|
||||
{
|
||||
const TestData *td = test_data;
|
||||
GString *cmd_line = g_string_new("-machine quanta-gsj");
|
||||
int *test_sockets = packet_test_init(emc_module_index(td->module),
|
||||
cmd_line);
|
||||
QTestState *qts = qtest_init(cmd_line->str);
|
||||
|
||||
/*
|
||||
* TODO: For pedantic correctness test_sockets[0] should be closed after
|
||||
* the fork and before the exec, but that will require some harness
|
||||
* improvements.
|
||||
*/
|
||||
close(test_sockets[1]);
|
||||
/* Defensive programming */
|
||||
test_sockets[1] = -1;
|
||||
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
|
||||
emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);
|
||||
emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
static void test_rx(gconstpointer test_data)
|
||||
{
|
||||
const TestData *td = test_data;
|
||||
GString *cmd_line = g_string_new("-machine quanta-gsj");
|
||||
int *test_sockets = packet_test_init(emc_module_index(td->module),
|
||||
cmd_line);
|
||||
QTestState *qts = qtest_init(cmd_line->str);
|
||||
|
||||
/*
|
||||
* TODO: For pedantic correctness test_sockets[0] should be closed after
|
||||
* the fork and before the exec, but that will require some harness
|
||||
* improvements.
|
||||
*/
|
||||
close(test_sockets[1]);
|
||||
/* Defensive programming */
|
||||
test_sockets[1] = -1;
|
||||
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
|
||||
emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);
|
||||
emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);
|
||||
emc_test_ptle(qts, td->module, test_sockets[0]);
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
static void emc_add_test(const char *name, const TestData* td,
|
||||
GTestDataFunc fn)
|
||||
{
|
||||
g_autofree char *full_name = g_strdup_printf(
|
||||
"npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name);
|
||||
qtest_add_data_func(full_name, td, fn);
|
||||
}
|
||||
#define add_test(name, td) emc_add_test(#name, td, test_##name)
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
TestData test_data_list[ARRAY_SIZE(emc_module_list)];
|
||||
|
||||
g_test_init(&argc, &argv, NULL);
|
||||
|
||||
for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) {
|
||||
TestData *td = &test_data_list[i];
|
||||
|
||||
td->module = &emc_module_list[i];
|
||||
|
||||
add_test(init, td);
|
||||
add_test(tx, td);
|
||||
add_test(rx, td);
|
||||
}
|
||||
|
||||
return g_test_run();
|
||||
}
|
||||
Loading…
Reference in New Issue