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riscv: Skip checking CSR privilege level in debugger mode 

If we are in debugger mode, skip the CSR privilege level checking
so that we can read/write all CSRs. Otherwise we get:

(gdb) p/x $mtvec
Could not fetch register "mtvec"; remote failure reply 'E14'

when the hart is currently in S-mode.

Reported-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-20 07:47:14 -07:00 committed by Palmer Dabbelt
parent 9bb7350232
commit e6e03dcffd
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1 changed files with 4 additions and 1 deletions
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5
target/riscv/csr.c
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@ -801,7 +801,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
#if !defined(CONFIG_USER_ONLY)
int csr_priv = get_field(csrno, 0x300);
int read_only = get_field(csrno, 0xC00) == 3;
if ((write_mask && read_only) || (env->priv < csr_priv)) {
if ((!env->debugger) && (env->priv < csr_priv)) {
return -1;
}
if (write_mask && read_only) {
return -1;
}
#endif