target-arm: Override do_interrupt for ARMv7-M profile
Enable ARMCPUInfo to specify a custom class_init functions. Introduce arm_v7m_class_init() and use it for "cortex-m3" model. Instead of forwarding from arm_cpu_do_interrupt() to do_interrupt_v7m(), override CPUClass::do_interrupt with arm_v7m_cpu_do_interrupt() in arm_v7m_class_init(). Acked-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
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@ -114,5 +114,6 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
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void register_cp_regs_for_features(ARMCPU *cpu);
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void register_cp_regs_for_features(ARMCPU *cpu);
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void arm_cpu_do_interrupt(CPUState *cpu);
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void arm_cpu_do_interrupt(CPUState *cpu);
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void arm_v7m_cpu_do_interrupt(CPUState *cpu);
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#endif
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#endif
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@ -412,6 +412,15 @@ static void cortex_m3_initfn(Object *obj)
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cpu->midr = 0x410fc231;
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cpu->midr = 0x410fc231;
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}
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}
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static void arm_v7m_class_init(ObjectClass *oc, void *data)
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{
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#ifndef CONFIG_USER_ONLY
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CPUClass *cc = CPU_CLASS(oc);
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cc->do_interrupt = arm_v7m_cpu_do_interrupt;
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#endif
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}
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
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{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
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{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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@ -752,6 +761,7 @@ static void arm_any_initfn(Object *obj)
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typedef struct ARMCPUInfo {
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typedef struct ARMCPUInfo {
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const char *name;
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const char *name;
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void (*initfn)(Object *obj);
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void (*initfn)(Object *obj);
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void (*class_init)(ObjectClass *oc, void *data);
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} ARMCPUInfo;
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} ARMCPUInfo;
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static const ARMCPUInfo arm_cpus[] = {
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static const ARMCPUInfo arm_cpus[] = {
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@ -766,7 +776,8 @@ static const ARMCPUInfo arm_cpus[] = {
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{ .name = "arm1136", .initfn = arm1136_initfn },
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{ .name = "arm1136", .initfn = arm1136_initfn },
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{ .name = "arm1176", .initfn = arm1176_initfn },
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{ .name = "arm1176", .initfn = arm1176_initfn },
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{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
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{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
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{ .name = "cortex-m3", .initfn = cortex_m3_initfn },
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{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
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{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
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{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
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{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
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{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
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{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
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@ -812,6 +823,7 @@ static void cpu_register(const ARMCPUInfo *info)
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.instance_size = sizeof(ARMCPU),
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.instance_size = sizeof(ARMCPU),
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.instance_init = info->initfn,
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.instance_init = info->initfn,
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.class_size = sizeof(ARMCPUClass),
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.class_size = sizeof(ARMCPUClass),
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.class_init = info->class_init,
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};
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};
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type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
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type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
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@ -1725,8 +1725,10 @@ static void do_v7m_exception_exit(CPUARMState *env)
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pointer. */
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pointer. */
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}
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}
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static void do_interrupt_v7m(CPUARMState *env)
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void arm_v7m_cpu_do_interrupt(CPUState *cs)
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{
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t xpsr = xpsr_read(env);
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uint32_t xpsr = xpsr_read(env);
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uint32_t lr;
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uint32_t lr;
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uint32_t addr;
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uint32_t addr;
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@ -1811,10 +1813,8 @@ void arm_cpu_do_interrupt(CPUState *cs)
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int new_mode;
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int new_mode;
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uint32_t offset;
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uint32_t offset;
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if (IS_M(env)) {
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assert(!IS_M(env));
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do_interrupt_v7m(env);
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return;
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}
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/* TODO: Vectored interrupt controller. */
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/* TODO: Vectored interrupt controller. */
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switch (env->exception_index) {
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switch (env->exception_index) {
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case EXCP_UDEF:
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case EXCP_UDEF:
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