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target-mips: use physical address in lladdr

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Currently the ll/sc instructions use the virtual address in both
user and system mode. Use the physical address insteead in system
mode.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2009-11-30 15:39:54 +01:00
parent 25b91e32e0
commit e7139c440c
3 changed files with 61 additions and 28 deletions
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9
target-mips/helper.h
View File

@ -15,6 +15,15 @@ DEF_HELPER_3(lwr, tl, tl, tl, int)
DEF_HELPER_3(swl, void, tl, tl, int)
DEF_HELPER_3(swr, void, tl, tl, int)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_2(ll, tl, tl, int)
DEF_HELPER_3(sc, tl, tl, tl, int)
#ifdef TARGET_MIPS64
DEF_HELPER_2(lld, tl, tl, int)
DEF_HELPER_3(scd, tl, tl, tl, int)
#endif
#endif
DEF_HELPER_FLAGS_1(clo, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
DEF_HELPER_FLAGS_1(clz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
#ifdef TARGET_MIPS64

39
target-mips/op_helper.c
View File

@ -275,6 +275,45 @@ void helper_dmultu (target_ulong arg1, target_ulong arg2)
}
#endif
#ifndef CONFIG_USER_ONLY
#define HELPER_LD_ATOMIC(name, insn) \
target_ulong helper_##name(target_ulong arg, int mem_idx) \
{ \
env->lladdr = do_translate_address(env, arg, 0); \
env->llval = do_##insn(arg, mem_idx); \
return env->llval; \
}
HELPER_LD_ATOMIC(ll, lw)
#ifdef TARGET_MIPS64
HELPER_LD_ATOMIC(lld, ld)
#endif
#undef HELPER_LD_ATOMIC
#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
{ \
target_long tmp; \
\
if (arg2 & almask) { \
env->CP0_BadVAddr = arg2; \
helper_raise_exception(EXCP_AdES); \
} \
if (do_translate_address(env, arg2, 1) == env->lladdr) { \
tmp = do_##ld_insn(arg2, mem_idx); \
if (tmp == env->llval) { \
do_##st_insn(arg2, arg1, mem_idx); \
return 1; \
} \
} \
return 0; \
}
HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
#ifdef TARGET_MIPS64
HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
#endif
#undef HELPER_ST_ATOMIC
#endif
#ifdef TARGET_WORDS_BIGENDIAN
#define GET_LMASK(v) ((v) & 3)
#define GET_OFFSET(addr, offset) (addr + (offset))

41
target-mips/translate.c
View File

@ -912,16 +912,24 @@ OP_ST(sd,st64);
#endif
#undef OP_ST
#ifdef CONFIG_USER_ONLY
#define OP_LD_ATOMIC(insn,fname) \
static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
{ \
TCGv t0 = tcg_temp_new(); \
tcg_gen_mov_tl(t0, arg1); \
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
tcg_temp_free(t0); \
}
#else
#define OP_LD_ATOMIC(insn,fname) \
static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
{ \
gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
}
#endif
OP_LD_ATOMIC(ll,ld32s);
#if defined(TARGET_MIPS64)
OP_LD_ATOMIC(lld,ld64);
@ -941,7 +949,7 @@ static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ct
tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
generate_exception(ctx, EXCP_AdES); \
gen_set_label(l1); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
@ -957,34 +965,11 @@ static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ct
static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
{ \
TCGv t0 = tcg_temp_new(); \
TCGv t1 = tcg_temp_new(); \
int l1 = gen_new_label(); \
int l2 = gen_new_label(); \
int l3 = gen_new_label(); \
\
tcg_gen_andi_tl(t0, arg2, almask); \
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
generate_exception(ctx, EXCP_AdES); \
gen_set_label(l1); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, llval)); \
tcg_gen_qemu_##ldname(t1, arg2, ctx->mem_idx); \
tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l2); \
tcg_temp_free(t1); \
tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
tcg_gen_movi_tl(t0, 1); \
gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
gen_store_gpr(t0, rt); \
tcg_gen_br(l3); \
gen_set_label(l2); \
tcg_gen_movi_tl(t0, 0); \
gen_store_gpr(t0, rt); \
gen_set_label(l3); \
tcg_temp_free(t0); \
}
#endif
OP_ST_ATOMIC(sc,st32,ld32s,0x3);
#if defined(TARGET_MIPS64)
OP_ST_ATOMIC(scd,st64,ld64,0x7);
@ -1137,7 +1122,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
opn = "swr";
break;
case OPC_LL:
save_cpu_state(ctx, 0);
save_cpu_state(ctx, 1);
op_ldst_ll(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "ll";
@ -1179,7 +1164,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
break;
#endif
case OPC_SC:
save_cpu_state(ctx, 0);
save_cpu_state(ctx, 1);
op_ldst_sc(t1, t0, rt, ctx);
opn = "sc";
break;