From e7c8afb9058f9d46a089a9fb75cccf996886249c Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 17 Oct 2012 01:28:35 +0200 Subject: [PATCH] target-sparc: fix FMOVr instruction Like the MOVr instruction, the FMOVr instruction has the condition encoded between bits 10 and 12. Cc: Blue Swirl Signed-off-by: Aurelien Jarno Signed-off-by: Blue Swirl --- target-sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 5df287629e..4321393688 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3176,7 +3176,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) #define FMOVR(sz) \ do { \ DisasCompare cmp; \ - cond = GET_FIELD_SP(insn, 14, 17); \ + cond = GET_FIELD_SP(insn, 10, 12); \ cpu_src1 = get_src1(dc, insn); \ gen_compare_reg(&cmp, cond, cpu_src1); \ gen_fmov##sz(dc, &cmp, rd, rs2); \