target/riscv: Fix relationship between V, Zve*, F and D
Add dependence chain: * V => Zve64d => Zve64f => Zve32f => F * V => Zve64d => D Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-6-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -743,12 +743,27 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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return;
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}
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if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
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error_setg(errp, "V extension requires D extension");
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/* The V vector extension depends on the Zve64d extension */
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if (cpu->cfg.ext_v) {
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cpu->cfg.ext_zve64d = true;
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}
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/* The Zve64d extension depends on the Zve64f extension */
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if (cpu->cfg.ext_zve64d) {
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cpu->cfg.ext_zve64f = true;
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}
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/* The Zve64f extension depends on the Zve32f extension */
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if (cpu->cfg.ext_zve64f) {
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cpu->cfg.ext_zve32f = true;
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}
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if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
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error_setg(errp, "Zve64d/V extensions require D extension");
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return;
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}
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if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
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if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
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error_setg(errp, "Zve32f/Zve64f extensions require F extension");
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return;
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}
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