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target/riscv: Fix relationship between V, Zve*, F and D 

Add dependence chain:
*  V => Zve64d => Zve64f => Zve32f => F
*  V => Zve64d => D

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-6-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Weiwei Li 2023-02-15 10:05:30 +08:00 committed by Palmer Dabbelt
parent a7336161f0
commit e7f0a803a7
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GPG Key ID: 2E1319F35FBB1889
1 changed files with 18 additions and 3 deletions
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21
target/riscv/cpu.c
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@ -743,12 +743,27 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
error_setg(errp, "V extension requires D extension");
/* The V vector extension depends on the Zve64d extension */
if (cpu->cfg.ext_v) {
cpu->cfg.ext_zve64d = true;
}
/* The Zve64d extension depends on the Zve64f extension */
if (cpu->cfg.ext_zve64d) {
cpu->cfg.ext_zve64f = true;
}
/* The Zve64f extension depends on the Zve32f extension */
if (cpu->cfg.ext_zve64f) {
cpu->cfg.ext_zve32f = true;
}
if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
error_setg(errp, "Zve64d/V extensions require D extension");
return;
}
if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}