virtio-gpu: scanout fix, live migration support
vmsvga: security fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJXVSCcAAoJEEy22O7T6HE4Zf4P/35npT1VyXPpT7of/4fF/2+k zD1mGkB6cd4Zv45A9XkiT9RtaJJdOVnjVNftPp2J7t063lccGUOqbzEohh5At6Bl dbtjjbl/WBl+gDRRGGsPT+vHSYkzUBXWaNUeAnph7bgqTaRAm6U18sEnZmdHo6+9 /Sdtb+hVcoPPrq9g9qspd3DU7anMdbjTMrPepkFVKozK0fHn+LRCDxS5RWFz51C2 bcQAgPqT1TBYzrrcz8oFCBuDnaxCqHrSiawB/oh6uZwtcG9GGJqYJiDOmvGzJbDN RIwWZeOLcOBF2BRNI2AY6abMJkMTcMztEn8iNU8lZmSswgJ6cS+4YBjCsQfCxrcR aipbzI405D03oWJGSZed08Ud7Prp+tRHnOk/IU6zX5uT84U/0PVKTgUB9/xwq7L7 LSKKQUgG6AwCwg5XNneoj2O6H8CgbQGdZ2BVAiN66bYF/6TDG6msXkVotyWttjfK Y8DbkHiwcNrbI8vcKed/VGSUEoidk/NljiGeflzgwPoVlB2dbr6LPov2HNHFW/0/ /3rRatJhLgucjSeIdDU63ze/4If119YYwtj9EykN/Yhizmjsx0+st6BCsgyTjJXj HQ/hAk9wGCc/vhILHVoGQ5NOUqcfS05plyBXKF+GREugN7t/RE/kdtob54NeSqmP Jr0v3GmCn1zfKS6sw/iu =pera -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20160606-1' into staging virtio-gpu: scanout fix, live migration support vmsvga: security fixes # gpg: Signature made Mon 06 Jun 2016 08:05:00 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vga-20160606-1: virtio-gpu: add live migration support vmsvga: don't process more than 1024 fifo commands at once vmsvga: shadow fifo registers vmsvga: add more fifo checks vmsvga: move fifo sanity checks to vmsvga_fifo_length virtio-gpu: fix scanout rectangles Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
e854d0cf78
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@ -284,7 +284,7 @@ static void virgl_resource_attach_backing(VirtIOGPU *g,
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VIRTIO_GPU_FILL_CMD(att_rb);
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trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
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ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, &res_iovs);
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ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, NULL, &res_iovs);
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if (ret != 0) {
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cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
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return;
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@ -22,6 +22,8 @@
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#include "qemu/log.h"
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#include "qapi/error.h"
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#define VIRTIO_GPU_VM_VERSION 1
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static struct virtio_gpu_simple_resource*
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virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id);
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@ -94,7 +96,7 @@ static void update_cursor_data_virgl(VirtIOGPU *g,
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static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor)
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{
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struct virtio_gpu_scanout *s;
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bool move = cursor->hdr.type != VIRTIO_GPU_CMD_MOVE_CURSOR;
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bool move = cursor->hdr.type == VIRTIO_GPU_CMD_MOVE_CURSOR;
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if (cursor->pos.scanout_id >= g->conf.max_outputs) {
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return;
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@ -107,7 +109,7 @@ static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor)
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move ? "move" : "update",
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cursor->resource_id);
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if (move) {
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if (!move) {
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if (!s->current_cursor) {
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s->current_cursor = cursor_alloc(64, 64);
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}
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@ -120,6 +122,11 @@ static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor)
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g, s, cursor->resource_id);
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}
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dpy_cursor_define(s->con, s->current_cursor);
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s->cursor = *cursor;
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} else {
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s->cursor.pos.x = cursor->pos.x;
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s->cursor.pos.y = cursor->pos.y;
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}
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dpy_mouse_set(s->con, cursor->pos.x, cursor->pos.y,
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cursor->resource_id ? 1 : 0);
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@ -495,6 +502,11 @@ static void virtio_gpu_resource_flush(VirtIOGPU *g,
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pixman_region_fini(&flush_region);
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}
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static void virtio_unref_resource(pixman_image_t *image, void *data)
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{
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pixman_image_unref(data);
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}
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static void virtio_gpu_set_scanout(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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@ -571,8 +583,15 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
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!= ((uint8_t *)pixman_image_get_data(res->image) + offset) ||
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scanout->width != ss.r.width ||
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scanout->height != ss.r.height) {
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pixman_image_t *rect;
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void *ptr = (uint8_t *)pixman_image_get_data(res->image) + offset;
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rect = pixman_image_create_bits(format, ss.r.width, ss.r.height, ptr,
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pixman_image_get_stride(res->image));
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pixman_image_ref(res->image);
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pixman_image_set_destroy_function(rect, virtio_unref_resource,
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res->image);
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/* realloc the surface ptr */
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scanout->ds = qemu_create_displaysurface_pixman(res->image);
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scanout->ds = qemu_create_displaysurface_pixman(rect);
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if (!scanout->ds) {
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cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
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return;
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@ -590,7 +609,7 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
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int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
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struct virtio_gpu_ctrl_command *cmd,
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struct iovec **iov)
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uint64_t **addr, struct iovec **iov)
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{
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struct virtio_gpu_mem_entry *ents;
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size_t esize, s;
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@ -616,10 +635,16 @@ int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
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}
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*iov = g_malloc0(sizeof(struct iovec) * ab->nr_entries);
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if (addr) {
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*addr = g_malloc0(sizeof(uint64_t) * ab->nr_entries);
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}
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for (i = 0; i < ab->nr_entries; i++) {
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hwaddr len = ents[i].length;
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(*iov)[i].iov_len = ents[i].length;
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(*iov)[i].iov_base = cpu_physical_memory_map(ents[i].addr, &len, 1);
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if (addr) {
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(*addr)[i] = ents[i].addr;
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}
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if (!(*iov)[i].iov_base || len != ents[i].length) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to map MMIO memory for"
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" resource %d element %d\n",
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@ -627,6 +652,10 @@ int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
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virtio_gpu_cleanup_mapping_iov(*iov, i);
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g_free(ents);
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*iov = NULL;
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if (addr) {
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g_free(*addr);
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*addr = NULL;
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}
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return -1;
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}
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}
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@ -650,6 +679,8 @@ static void virtio_gpu_cleanup_mapping(struct virtio_gpu_simple_resource *res)
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virtio_gpu_cleanup_mapping_iov(res->iov, res->iov_cnt);
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res->iov = NULL;
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res->iov_cnt = 0;
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g_free(res->addrs);
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res->addrs = NULL;
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}
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static void
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@ -671,7 +702,7 @@ virtio_gpu_resource_attach_backing(VirtIOGPU *g,
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return;
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}
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ret = virtio_gpu_create_mapping_iov(&ab, cmd, &res->iov);
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ret = virtio_gpu_create_mapping_iov(&ab, cmd, &res->addrs, &res->iov);
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if (ret != 0) {
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cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
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return;
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@ -917,11 +948,163 @@ const GraphicHwOps virtio_gpu_ops = {
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.gl_block = virtio_gpu_gl_block,
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};
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static const VMStateDescription vmstate_virtio_gpu_scanout = {
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.name = "virtio-gpu-one-scanout",
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(resource_id, struct virtio_gpu_scanout),
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VMSTATE_UINT32(width, struct virtio_gpu_scanout),
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VMSTATE_UINT32(height, struct virtio_gpu_scanout),
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VMSTATE_INT32(x, struct virtio_gpu_scanout),
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VMSTATE_INT32(y, struct virtio_gpu_scanout),
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VMSTATE_UINT32(cursor.resource_id, struct virtio_gpu_scanout),
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VMSTATE_UINT32(cursor.hot_x, struct virtio_gpu_scanout),
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VMSTATE_UINT32(cursor.hot_y, struct virtio_gpu_scanout),
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VMSTATE_UINT32(cursor.pos.x, struct virtio_gpu_scanout),
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VMSTATE_UINT32(cursor.pos.y, struct virtio_gpu_scanout),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_virtio_gpu_scanouts = {
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.name = "virtio-gpu-scanouts",
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(enable, struct VirtIOGPU),
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VMSTATE_UINT32_EQUAL(conf.max_outputs, struct VirtIOGPU),
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VMSTATE_STRUCT_VARRAY_UINT32(scanout, struct VirtIOGPU,
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conf.max_outputs, 1,
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vmstate_virtio_gpu_scanout,
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struct virtio_gpu_scanout),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_virtio_gpu_unmigratable = {
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.name = "virtio-gpu",
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.name = "virtio-gpu-with-virgl",
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.unmigratable = 1,
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};
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static void virtio_gpu_save(QEMUFile *f, void *opaque)
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{
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VirtIOGPU *g = opaque;
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VirtIODevice *vdev = VIRTIO_DEVICE(g);
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struct virtio_gpu_simple_resource *res;
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int i;
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virtio_save(vdev, f);
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/* in 2d mode we should never find unprocessed commands here */
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assert(QTAILQ_EMPTY(&g->cmdq));
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QTAILQ_FOREACH(res, &g->reslist, next) {
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qemu_put_be32(f, res->resource_id);
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qemu_put_be32(f, res->width);
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qemu_put_be32(f, res->height);
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qemu_put_be32(f, res->format);
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qemu_put_be32(f, res->iov_cnt);
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for (i = 0; i < res->iov_cnt; i++) {
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qemu_put_be64(f, res->addrs[i]);
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qemu_put_be32(f, res->iov[i].iov_len);
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}
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qemu_put_buffer(f, (void *)pixman_image_get_data(res->image),
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pixman_image_get_stride(res->image) * res->height);
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}
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qemu_put_be32(f, 0); /* end of list */
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vmstate_save_state(f, &vmstate_virtio_gpu_scanouts, g, NULL);
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}
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static int virtio_gpu_load(QEMUFile *f, void *opaque, int version_id)
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{
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VirtIOGPU *g = opaque;
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VirtIODevice *vdev = VIRTIO_DEVICE(g);
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struct virtio_gpu_simple_resource *res;
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struct virtio_gpu_scanout *scanout;
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uint32_t resource_id, pformat;
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int i, ret;
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if (version_id != VIRTIO_GPU_VM_VERSION) {
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return -EINVAL;
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}
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ret = virtio_load(vdev, f, version_id);
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if (ret) {
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return ret;
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}
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resource_id = qemu_get_be32(f);
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while (resource_id != 0) {
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res = g_new0(struct virtio_gpu_simple_resource, 1);
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res->resource_id = resource_id;
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res->width = qemu_get_be32(f);
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res->height = qemu_get_be32(f);
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res->format = qemu_get_be32(f);
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res->iov_cnt = qemu_get_be32(f);
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/* allocate */
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pformat = get_pixman_format(res->format);
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if (!pformat) {
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return -EINVAL;
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}
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res->image = pixman_image_create_bits(pformat,
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res->width, res->height,
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NULL, 0);
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if (!res->image) {
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return -EINVAL;
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}
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res->addrs = g_new(uint64_t, res->iov_cnt);
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res->iov = g_new(struct iovec, res->iov_cnt);
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/* read data */
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for (i = 0; i < res->iov_cnt; i++) {
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res->addrs[i] = qemu_get_be64(f);
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res->iov[i].iov_len = qemu_get_be32(f);
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}
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qemu_get_buffer(f, (void *)pixman_image_get_data(res->image),
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pixman_image_get_stride(res->image) * res->height);
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/* restore mapping */
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for (i = 0; i < res->iov_cnt; i++) {
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hwaddr len = res->iov[i].iov_len;
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res->iov[i].iov_base =
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cpu_physical_memory_map(res->addrs[i], &len, 1);
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if (!res->iov[i].iov_base || len != res->iov[i].iov_len) {
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return -EINVAL;
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}
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}
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QTAILQ_INSERT_HEAD(&g->reslist, res, next);
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resource_id = qemu_get_be32(f);
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}
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/* load & apply scanout state */
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vmstate_load_state(f, &vmstate_virtio_gpu_scanouts, g, 1);
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for (i = 0; i < g->conf.max_outputs; i++) {
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scanout = &g->scanout[i];
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if (!scanout->resource_id) {
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continue;
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}
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res = virtio_gpu_find_resource(g, scanout->resource_id);
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if (!res) {
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return -EINVAL;
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}
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scanout->ds = qemu_create_displaysurface_pixman(res->image);
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if (!scanout->ds) {
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return -EINVAL;
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}
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dpy_gfx_replace_surface(scanout->con, scanout->ds);
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dpy_gfx_update(scanout->con, 0, 0, scanout->width, scanout->height);
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update_cursor(g, &scanout->cursor);
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res->scanout_bitmask |= (1 << i);
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}
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return 0;
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}
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static void virtio_gpu_device_realize(DeviceState *qdev, Error **errp)
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{
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VirtIODevice *vdev = VIRTIO_DEVICE(qdev);
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|
@ -979,7 +1162,12 @@ static void virtio_gpu_device_realize(DeviceState *qdev, Error **errp)
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}
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}
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vmstate_register(qdev, -1, &vmstate_virtio_gpu_unmigratable, g);
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if (virtio_gpu_virgl_enabled(g->conf)) {
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vmstate_register(qdev, -1, &vmstate_virtio_gpu_unmigratable, g);
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} else {
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register_savevm(qdev, "virtio-gpu", -1, VIRTIO_GPU_VM_VERSION,
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virtio_gpu_save, virtio_gpu_load, g);
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}
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}
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|
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static void virtio_gpu_instance_init(Object *obj)
|
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|
|
|
@ -84,6 +84,17 @@ static const GraphicHwOps virtio_vga_ops = {
|
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.gl_block = virtio_vga_gl_block,
|
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};
|
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|
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static const VMStateDescription vmstate_virtio_vga = {
|
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.name = "virtio-vga",
|
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.version_id = 2,
|
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.minimum_version_id = 2,
|
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.fields = (VMStateField[]) {
|
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/* no pci stuff here, saving the virtio device will handle that */
|
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VMSTATE_STRUCT(vga, VirtIOVGA, 0, vmstate_vga_common, VGACommonState),
|
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VMSTATE_END_OF_LIST()
|
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}
|
||||
};
|
||||
|
||||
/* VGA device wrapper around PCI device around virtio GPU */
|
||||
static void virtio_vga_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
|
||||
{
|
||||
|
@ -168,6 +179,7 @@ static void virtio_vga_class_init(ObjectClass *klass, void *data)
|
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set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
|
||||
dc->props = virtio_vga_properties;
|
||||
dc->reset = virtio_vga_reset;
|
||||
dc->vmsd = &vmstate_virtio_vga;
|
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dc->hotpluggable = false;
|
||||
|
||||
k->realize = virtio_vga_realize;
|
||||
|
|
|
@ -66,17 +66,11 @@ struct vmsvga_state_s {
|
|||
uint8_t *fifo_ptr;
|
||||
unsigned int fifo_size;
|
||||
|
||||
union {
|
||||
uint32_t *fifo;
|
||||
struct QEMU_PACKED {
|
||||
uint32_t min;
|
||||
uint32_t max;
|
||||
uint32_t next_cmd;
|
||||
uint32_t stop;
|
||||
/* Add registers here when adding capabilities. */
|
||||
uint32_t fifo[0];
|
||||
} *cmd;
|
||||
};
|
||||
uint32_t *fifo;
|
||||
uint32_t fifo_min;
|
||||
uint32_t fifo_max;
|
||||
uint32_t fifo_next;
|
||||
uint32_t fifo_stop;
|
||||
|
||||
#define REDRAW_FIFO_LEN 512
|
||||
struct vmsvga_rect_s {
|
||||
|
@ -198,7 +192,7 @@ enum {
|
|||
*/
|
||||
SVGA_FIFO_MIN = 0,
|
||||
SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
|
||||
SVGA_FIFO_NEXT_CMD,
|
||||
SVGA_FIFO_NEXT,
|
||||
SVGA_FIFO_STOP,
|
||||
|
||||
/*
|
||||
|
@ -546,8 +540,6 @@ static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
|
|||
}
|
||||
#endif
|
||||
|
||||
#define CMD(f) le32_to_cpu(s->cmd->f)
|
||||
|
||||
static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
|
||||
{
|
||||
int num;
|
||||
|
@ -555,21 +547,45 @@ static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
|
|||
if (!s->config || !s->enable) {
|
||||
return 0;
|
||||
}
|
||||
num = CMD(next_cmd) - CMD(stop);
|
||||
|
||||
s->fifo_min = le32_to_cpu(s->fifo[SVGA_FIFO_MIN]);
|
||||
s->fifo_max = le32_to_cpu(s->fifo[SVGA_FIFO_MAX]);
|
||||
s->fifo_next = le32_to_cpu(s->fifo[SVGA_FIFO_NEXT]);
|
||||
s->fifo_stop = le32_to_cpu(s->fifo[SVGA_FIFO_STOP]);
|
||||
|
||||
/* Check range and alignment. */
|
||||
if ((s->fifo_min | s->fifo_max | s->fifo_next | s->fifo_stop) & 3) {
|
||||
return 0;
|
||||
}
|
||||
if (s->fifo_min < sizeof(uint32_t) * 4) {
|
||||
return 0;
|
||||
}
|
||||
if (s->fifo_max > SVGA_FIFO_SIZE ||
|
||||
s->fifo_min >= SVGA_FIFO_SIZE ||
|
||||
s->fifo_stop >= SVGA_FIFO_SIZE ||
|
||||
s->fifo_next >= SVGA_FIFO_SIZE) {
|
||||
return 0;
|
||||
}
|
||||
if (s->fifo_max < s->fifo_min + 10 * 1024) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
num = s->fifo_next - s->fifo_stop;
|
||||
if (num < 0) {
|
||||
num += CMD(max) - CMD(min);
|
||||
num += s->fifo_max - s->fifo_min;
|
||||
}
|
||||
return num >> 2;
|
||||
}
|
||||
|
||||
static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
|
||||
{
|
||||
uint32_t cmd = s->fifo[CMD(stop) >> 2];
|
||||
uint32_t cmd = s->fifo[s->fifo_stop >> 2];
|
||||
|
||||
s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
|
||||
if (CMD(stop) >= CMD(max)) {
|
||||
s->cmd->stop = s->cmd->min;
|
||||
s->fifo_stop += 4;
|
||||
if (s->fifo_stop >= s->fifo_max) {
|
||||
s->fifo_stop = s->fifo_min;
|
||||
}
|
||||
s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop);
|
||||
return cmd;
|
||||
}
|
||||
|
||||
|
@ -581,15 +597,15 @@ static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
|
|||
static void vmsvga_fifo_run(struct vmsvga_state_s *s)
|
||||
{
|
||||
uint32_t cmd, colour;
|
||||
int args, len;
|
||||
int args, len, maxloop = 1024;
|
||||
int x, y, dx, dy, width, height;
|
||||
struct vmsvga_cursor_definition_s cursor;
|
||||
uint32_t cmd_start;
|
||||
|
||||
len = vmsvga_fifo_length(s);
|
||||
while (len > 0) {
|
||||
while (len > 0 && --maxloop > 0) {
|
||||
/* May need to go back to the start of the command if incomplete */
|
||||
cmd_start = s->cmd->stop;
|
||||
cmd_start = s->fifo_stop;
|
||||
|
||||
switch (cmd = vmsvga_fifo_read(s)) {
|
||||
case SVGA_CMD_UPDATE:
|
||||
|
@ -748,7 +764,8 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s)
|
|||
break;
|
||||
|
||||
rewind:
|
||||
s->cmd->stop = cmd_start;
|
||||
s->fifo_stop = cmd_start;
|
||||
s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -1005,19 +1022,6 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
|
|||
case SVGA_REG_CONFIG_DONE:
|
||||
if (value) {
|
||||
s->fifo = (uint32_t *) s->fifo_ptr;
|
||||
/* Check range and alignment. */
|
||||
if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {
|
||||
break;
|
||||
}
|
||||
if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
|
||||
break;
|
||||
}
|
||||
if (CMD(max) > SVGA_FIFO_SIZE) {
|
||||
break;
|
||||
}
|
||||
if (CMD(max) < CMD(min) + 10 * 1024) {
|
||||
break;
|
||||
}
|
||||
vga_dirty_log_stop(&s->vga);
|
||||
}
|
||||
s->config = !!value;
|
||||
|
|
|
@ -32,6 +32,7 @@ struct virtio_gpu_simple_resource {
|
|||
uint32_t width;
|
||||
uint32_t height;
|
||||
uint32_t format;
|
||||
uint64_t *addrs;
|
||||
struct iovec *iov;
|
||||
unsigned int iov_cnt;
|
||||
uint32_t scanout_bitmask;
|
||||
|
@ -46,6 +47,7 @@ struct virtio_gpu_scanout {
|
|||
int x, y;
|
||||
int invalidate;
|
||||
uint32_t resource_id;
|
||||
struct virtio_gpu_update_cursor cursor;
|
||||
QEMUCursor *current_cursor;
|
||||
};
|
||||
|
||||
|
@ -150,7 +152,7 @@ void virtio_gpu_get_display_info(VirtIOGPU *g,
|
|||
struct virtio_gpu_ctrl_command *cmd);
|
||||
int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
|
||||
struct virtio_gpu_ctrl_command *cmd,
|
||||
struct iovec **iov);
|
||||
uint64_t **addr, struct iovec **iov);
|
||||
void virtio_gpu_cleanup_mapping_iov(struct iovec *iov, uint32_t count);
|
||||
void virtio_gpu_process_cmdq(VirtIOGPU *g);
|
||||
|
||||
|
|
Loading…
Reference in New Issue