tcg/tci: Split out tci_args_rrr
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
fc4a62f65c
commit
e85e4b8f95
154
tcg/tci.c
154
tcg/tci.c
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@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr,
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*r1 = tci_read_r(tb_ptr);
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}
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static void tci_args_rrr(const uint8_t **tb_ptr,
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TCGReg *r0, TCGReg *r1, TCGReg *r2)
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{
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*r0 = tci_read_r(tb_ptr);
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*r1 = tci_read_r(tb_ptr);
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*r2 = tci_read_r(tb_ptr);
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}
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static void tci_args_rrs(const uint8_t **tb_ptr,
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TCGReg *r0, TCGReg *r1, int32_t *i2)
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{
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@ -349,7 +357,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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uint8_t op_size = tb_ptr[1];
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const uint8_t *old_code_ptr = tb_ptr;
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#endif
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TCGReg r0, r1;
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TCGReg r0, r1, r2;
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tcg_target_ulong t0;
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tcg_target_ulong t1;
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tcg_target_ulong t2;
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@ -486,101 +494,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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/* Arithmetic operations (mixed 32/64 bit). */
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CASE_32_64(add)
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1 + t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = regs[r1] + regs[r2];
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break;
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CASE_32_64(sub)
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1 - t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = regs[r1] - regs[r2];
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break;
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CASE_32_64(mul)
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1 * t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = regs[r1] * regs[r2];
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break;
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CASE_32_64(and)
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1 & t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = regs[r1] & regs[r2];
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break;
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CASE_32_64(or)
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1 | t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = regs[r1] | regs[r2];
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break;
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CASE_32_64(xor)
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1 ^ t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = regs[r1] ^ regs[r2];
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break;
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/* Arithmetic operations (32 bit). */
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case INDEX_op_div_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
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break;
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case INDEX_op_divu_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
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break;
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case INDEX_op_rem_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2];
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break;
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case INDEX_op_remu_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
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break;
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/* Shift/rotate operations (32 bit). */
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case INDEX_op_shl_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
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break;
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case INDEX_op_shr_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
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break;
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case INDEX_op_sar_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
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break;
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#if TCG_TARGET_HAS_rot_i32
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case INDEX_op_rotl_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, rol32(t1, t2 & 31));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = rol32(regs[r1], regs[r2] & 31);
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break;
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case INDEX_op_rotr_i32:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, ror32(t1, t2 & 31));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = ror32(regs[r1], regs[r2] & 31);
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break;
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#endif
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#if TCG_TARGET_HAS_deposit_i32
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@ -715,62 +693,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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/* Arithmetic operations (64 bit). */
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case INDEX_op_div_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2];
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break;
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case INDEX_op_divu_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2];
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break;
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case INDEX_op_rem_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2];
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break;
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case INDEX_op_remu_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
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break;
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/* Shift/rotate operations (64 bit). */
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case INDEX_op_shl_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1 << (t2 & 63));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = regs[r1] << (regs[r2] & 63);
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break;
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case INDEX_op_shr_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1 >> (t2 & 63));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = regs[r1] >> (regs[r2] & 63);
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break;
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case INDEX_op_sar_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
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break;
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#if TCG_TARGET_HAS_rot_i64
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case INDEX_op_rotl_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, rol64(t1, t2 & 63));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = rol64(regs[r1], regs[r2] & 63);
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break;
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case INDEX_op_rotr_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_rval(regs, &tb_ptr);
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t2 = tci_read_rval(regs, &tb_ptr);
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tci_write_reg(regs, t0, ror64(t1, t2 & 63));
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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regs[r0] = ror64(regs[r1], regs[r2] & 63);
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break;
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#endif
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#if TCG_TARGET_HAS_deposit_i64
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