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qemu/timer: Add host ticks function for RISC-V

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Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230911063223.742-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
LIU Zhiwei 2023-09-11 14:32:23 +08:00 committed by Paolo Bonzini
parent 3a2a1f97ea
commit e8eed838ec
1 changed files with 22 additions and 0 deletions
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22
include/qemu/timer.h
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@ -979,6 +979,28 @@ static inline int64_t cpu_get_host_ticks(void)
return cur - ofs;
}
#elif defined(__riscv) && __riscv_xlen == 32
static inline int64_t cpu_get_host_ticks(void)
{
uint32_t lo, hi, tmph;
do {
asm volatile("RDTIMEH %0\n\t"
"RDTIME %1\n\t"
"RDTIMEH %2"
: "=r"(hi), "=r"(lo), "=r"(tmph));
} while (unlikely(tmph != hi));
return lo | (uint64_t)hi << 32;
}
#elif defined(__riscv) && __riscv_xlen > 32
static inline int64_t cpu_get_host_ticks(void)
{
int64_t val;
asm volatile("RDTIME %0" : "=r"(val));
return val;
}
#else
/* The host CPU doesn't have an easily accessible cycle counter.
Just return a monotonically increasing value. This will be