target/ppc: Move D/DS/X-form integer stores to decodetree
These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-9-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson
David Gibson
parent
00e0326541
commit
e8f4c8d6aa
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@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 @DS
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LDX 011111 ..... ..... ..... 0000010101 - @X
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LDUX 011111 ..... ..... ..... 0000110101 - @X
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### Fixed-Point Store Instructions
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STB 100110 ..... ..... ................ @D
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STBU 100111 ..... ..... ................ @D
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STBX 011111 ..... ..... ..... 0011010111 - @X
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STBUX 011111 ..... ..... ..... 0011110111 - @X
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STH 101100 ..... ..... ................ @D
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STHU 101101 ..... ..... ................ @D
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STHX 011111 ..... ..... ..... 0110010111 - @X
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STHUX 011111 ..... ..... ..... 0110110111 - @X
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STW 100100 ..... ..... ................ @D
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STWU 100101 ..... ..... ................ @D
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STWX 011111 ..... ..... ..... 0010010111 - @X
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STWUX 011111 ..... ..... ..... 0010110111 - @X
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STD 111110 ..... ..... ..............00 @DS
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STDU 111110 ..... ..... ..............01 @DS
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STDX 011111 ..... ..... ..... 0010010101 - @X
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STDUX 011111 ..... ..... ..... 0010110101 - @X
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### Fixed-Point Arithmetic Instructions
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ADDI 001110 ..... ..... ................ @D
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@ -3299,7 +3299,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \
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tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
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}
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#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
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GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
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#endif
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GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
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GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
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@ -3432,52 +3434,6 @@ static void gen_lq(DisasContext *ctx)
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#endif
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/*** Integer store ***/
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#define GEN_ST(name, stop, opc, type) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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gen_set_access_type(ctx, ACCESS_INT); \
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EA = tcg_temp_new(); \
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gen_addr_imm_index(ctx, EA, 0); \
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gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
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tcg_temp_free(EA); \
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}
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#define GEN_STU(name, stop, opc, type) \
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static void glue(gen_, stop##u)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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if (unlikely(rA(ctx->opcode) == 0)) { \
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_INT); \
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EA = tcg_temp_new(); \
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if (type == PPC_64B) \
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gen_addr_imm_index(ctx, EA, 0x03); \
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else \
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gen_addr_imm_index(ctx, EA, 0); \
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gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
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tcg_temp_free(EA); \
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}
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#define GEN_STUX(name, stop, opc2, opc3, type) \
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static void glue(gen_, name##ux)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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if (unlikely(rA(ctx->opcode) == 0)) { \
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_INT); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
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tcg_temp_free(EA); \
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}
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#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
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static void glue(gen_, name##x)(DisasContext *ctx) \
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{ \
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@ -3495,19 +3451,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
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#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
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GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
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#define GEN_STS(name, stop, op, type) \
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GEN_ST(name, stop, op | 0x20, type); \
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GEN_STU(name, stop, op | 0x21, type); \
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GEN_STUX(name, stop, 0x17, op | 0x01, type); \
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GEN_STX(name, stop, 0x17, op | 0x00, type)
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/* stb stbu stbux stbx */
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GEN_STS(stb, st8, 0x06, PPC_INTEGER);
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/* sth sthu sthux sthx */
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GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
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/* stw stwu stwux stwx */
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GEN_STS(stw, st32, 0x04, PPC_INTEGER);
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#define GEN_STEPX(name, stop, opc2, opc3) \
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static void glue(gen_, name##epx)(DisasContext *ctx) \
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{ \
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@ -3529,8 +3472,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
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#endif
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#if defined(TARGET_PPC64)
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GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
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GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
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GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
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GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
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GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
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@ -8166,31 +8107,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
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GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
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#endif
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#undef GEN_ST
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#undef GEN_STU
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#undef GEN_STUX
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#undef GEN_STX_E
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#undef GEN_STS
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#define GEN_ST(name, stop, opc, type) \
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GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
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#define GEN_STU(name, stop, opc, type) \
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GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
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#define GEN_STUX(name, stop, opc2, opc3, type) \
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GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
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#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
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GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
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#define GEN_STS(name, stop, op, type) \
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GEN_ST(name, stop, op | 0x20, type) \
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GEN_STU(name, stop, op | 0x21, type) \
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GEN_STUX(name, stop, 0x17, op | 0x01, type) \
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GEN_STX(name, stop, 0x17, op | 0x00, type)
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GEN_STS(stb, st8, 0x06, PPC_INTEGER)
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GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
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GEN_STS(stw, st32, 0x04, PPC_INTEGER)
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#if defined(TARGET_PPC64)
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GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
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GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
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GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
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GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
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GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
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@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
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TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
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TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
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/* Store Byte */
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TRANS(STB, do_ldst_D, false, true, MO_UB)
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TRANS(STBX, do_ldst_X, false, true, MO_UB)
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TRANS(STBU, do_ldst_D, true, true, MO_UB)
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TRANS(STBUX, do_ldst_X, true, true, MO_UB)
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/* Store Halfword */
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TRANS(STH, do_ldst_D, false, true, MO_UW)
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TRANS(STHX, do_ldst_X, false, true, MO_UW)
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TRANS(STHU, do_ldst_D, true, true, MO_UW)
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TRANS(STHUX, do_ldst_X, true, true, MO_UW)
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/* Store Word */
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TRANS(STW, do_ldst_D, false, true, MO_UL)
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TRANS(STWX, do_ldst_X, false, true, MO_UL)
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TRANS(STWU, do_ldst_D, true, true, MO_UL)
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TRANS(STWUX, do_ldst_X, true, true, MO_UL)
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/* Store Doubleword */
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TRANS64(STD, do_ldst_D, false, true, MO_Q)
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TRANS64(STDX, do_ldst_X, false, true, MO_Q)
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TRANS64(STDU, do_ldst_D, true, true, MO_Q)
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TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
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/*
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* Fixed-Point Arithmetic Instructions
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*/
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