target-ppc: Altivec 2.07: Binary Coded Decimal Instructions
This patch add the Binary Coded Decimal instructions bcdadd. and bcdsub. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta
Alexander Graf
parent
b8476fc7c6
commit
e8f7b27b99
@ -316,6 +316,9 @@ DEF_HELPER_3(vpmsumh, void, avr, avr, avr)
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DEF_HELPER_3(vpmsumw, void, avr, avr, avr)
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DEF_HELPER_3(vpmsumd, void, avr, avr, avr)
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DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
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DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
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DEF_HELPER_2(xsadddp, void, env, i32)
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DEF_HELPER_2(xssubdp, void, env, i32)
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DEF_HELPER_2(xsmuldp, void, env, i32)
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@ -2136,6 +2136,207 @@ void helper_vsubecuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
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#endif
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}
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#define BCD_PLUS_PREF_1 0xC
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#define BCD_PLUS_PREF_2 0xF
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#define BCD_PLUS_ALT_1 0xA
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#define BCD_NEG_PREF 0xD
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#define BCD_NEG_ALT 0xB
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#define BCD_PLUS_ALT_2 0xE
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#if defined(HOST_WORDS_BIGENDIAN)
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#define BCD_DIG_BYTE(n) (15 - (n/2))
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#else
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#define BCD_DIG_BYTE(n) (n/2)
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#endif
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static int bcd_get_sgn(ppc_avr_t *bcd)
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{
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switch (bcd->u8[BCD_DIG_BYTE(0)] & 0xF) {
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case BCD_PLUS_PREF_1:
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case BCD_PLUS_PREF_2:
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case BCD_PLUS_ALT_1:
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case BCD_PLUS_ALT_2:
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{
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return 1;
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}
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case BCD_NEG_PREF:
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case BCD_NEG_ALT:
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{
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return -1;
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}
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default:
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{
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return 0;
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}
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}
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}
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static int bcd_preferred_sgn(int sgn, int ps)
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{
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if (sgn >= 0) {
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return (ps == 0) ? BCD_PLUS_PREF_1 : BCD_PLUS_PREF_2;
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} else {
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return BCD_NEG_PREF;
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}
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}
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static uint8_t bcd_get_digit(ppc_avr_t *bcd, int n, int *invalid)
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{
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uint8_t result;
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if (n & 1) {
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result = bcd->u8[BCD_DIG_BYTE(n)] >> 4;
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} else {
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result = bcd->u8[BCD_DIG_BYTE(n)] & 0xF;
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}
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if (unlikely(result > 9)) {
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*invalid = true;
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}
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return result;
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}
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static void bcd_put_digit(ppc_avr_t *bcd, uint8_t digit, int n)
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{
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if (n & 1) {
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bcd->u8[BCD_DIG_BYTE(n)] &= 0x0F;
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bcd->u8[BCD_DIG_BYTE(n)] |= (digit<<4);
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} else {
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bcd->u8[BCD_DIG_BYTE(n)] &= 0xF0;
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bcd->u8[BCD_DIG_BYTE(n)] |= digit;
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}
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}
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static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b)
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{
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int i;
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int invalid = 0;
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for (i = 31; i > 0; i--) {
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uint8_t dig_a = bcd_get_digit(a, i, &invalid);
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uint8_t dig_b = bcd_get_digit(b, i, &invalid);
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if (unlikely(invalid)) {
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return 0; /* doesnt matter */
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} else if (dig_a > dig_b) {
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return 1;
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} else if (dig_a < dig_b) {
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return -1;
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}
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}
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return 0;
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}
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static int bcd_add_mag(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, int *invalid,
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int *overflow)
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{
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int carry = 0;
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int i;
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int is_zero = 1;
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for (i = 1; i <= 31; i++) {
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uint8_t digit = bcd_get_digit(a, i, invalid) +
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bcd_get_digit(b, i, invalid) + carry;
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is_zero &= (digit == 0);
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if (digit > 9) {
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carry = 1;
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digit -= 10;
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} else {
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carry = 0;
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}
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bcd_put_digit(t, digit, i);
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if (unlikely(*invalid)) {
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return -1;
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}
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}
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*overflow = carry;
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return is_zero;
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}
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static int bcd_sub_mag(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, int *invalid,
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int *overflow)
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{
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int carry = 0;
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int i;
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int is_zero = 1;
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for (i = 1; i <= 31; i++) {
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uint8_t digit = bcd_get_digit(a, i, invalid) -
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bcd_get_digit(b, i, invalid) + carry;
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is_zero &= (digit == 0);
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if (digit & 0x80) {
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carry = -1;
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digit += 10;
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} else {
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carry = 0;
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}
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bcd_put_digit(t, digit, i);
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if (unlikely(*invalid)) {
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return -1;
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}
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}
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*overflow = carry;
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return is_zero;
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}
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uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
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{
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int sgna = bcd_get_sgn(a);
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int sgnb = bcd_get_sgn(b);
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int invalid = (sgna == 0) || (sgnb == 0);
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int overflow = 0;
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int zero = 0;
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uint32_t cr = 0;
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ppc_avr_t result = { .u64 = { 0, 0 } };
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if (!invalid) {
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if (sgna == sgnb) {
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result.u8[BCD_DIG_BYTE(0)] = bcd_preferred_sgn(sgna, ps);
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zero = bcd_add_mag(&result, a, b, &invalid, &overflow);
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cr = (sgna > 0) ? 4 : 8;
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} else if (bcd_cmp_mag(a, b) > 0) {
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result.u8[BCD_DIG_BYTE(0)] = bcd_preferred_sgn(sgna, ps);
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zero = bcd_sub_mag(&result, a, b, &invalid, &overflow);
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cr = (sgna > 0) ? 4 : 8;
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} else {
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result.u8[BCD_DIG_BYTE(0)] = bcd_preferred_sgn(sgnb, ps);
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zero = bcd_sub_mag(&result, b, a, &invalid, &overflow);
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cr = (sgnb > 0) ? 4 : 8;
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}
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}
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if (unlikely(invalid)) {
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result.u64[HI_IDX] = result.u64[LO_IDX] = -1;
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cr = 1;
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} else if (overflow) {
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cr |= 1;
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} else if (zero) {
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cr = 2;
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}
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*r = result;
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return cr;
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}
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uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
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{
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ppc_avr_t bcopy = *b;
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int sgnb = bcd_get_sgn(b);
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if (sgnb < 0) {
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bcd_put_digit(&bcopy, BCD_PLUS_PREF_1, 0);
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} else if (sgnb > 0) {
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bcd_put_digit(&bcopy, BCD_NEG_PREF, 0);
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}
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/* else invalid ... defer to bcdadd code for proper handling */
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return helper_bcdadd(r, a, &bcopy, ps);
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}
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#undef VECTOR_FOR_INORDER_I
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#undef HI_IDX
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@ -7377,6 +7377,43 @@ GEN_VXFORM(vpmsumh, 4, 17)
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GEN_VXFORM(vpmsumw, 4, 18)
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GEN_VXFORM(vpmsumd, 4, 19)
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#define GEN_BCD(op) \
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static void gen_##op(DisasContext *ctx) \
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{ \
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TCGv_ptr ra, rb, rd; \
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TCGv_i32 ps; \
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\
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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} \
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\
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ra = gen_avr_ptr(rA(ctx->opcode)); \
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rb = gen_avr_ptr(rB(ctx->opcode)); \
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rd = gen_avr_ptr(rD(ctx->opcode)); \
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\
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ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
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\
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gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
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\
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(rb); \
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tcg_temp_free_ptr(rd); \
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tcg_temp_free_i32(ps); \
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}
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GEN_BCD(bcdadd)
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GEN_BCD(bcdsub)
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GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
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bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
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GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
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bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
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GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
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bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
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GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
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bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
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/*** VSX extension ***/
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static inline TCGv_i64 cpu_vsrh(int n)
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@ -10442,8 +10479,8 @@ GEN_VXFORM(vaddubm, 0, 0),
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GEN_VXFORM(vadduhm, 0, 1),
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GEN_VXFORM(vadduwm, 0, 2),
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GEN_VXFORM_207(vaddudm, 0, 3),
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GEN_VXFORM(vsububm, 0, 16),
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GEN_VXFORM(vsubuhm, 0, 17),
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GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM(vsubuwm, 0, 18),
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GEN_VXFORM_207(vsubudm, 0, 19),
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GEN_VXFORM(vmaxub, 1, 0),
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@ -10510,8 +10547,8 @@ GEN_VXFORM(vadduws, 0, 10),
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GEN_VXFORM(vaddsbs, 0, 12),
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GEN_VXFORM(vaddshs, 0, 13),
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GEN_VXFORM(vaddsws, 0, 14),
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GEN_VXFORM(vsububs, 0, 24),
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GEN_VXFORM(vsubuhs, 0, 25),
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GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM(vsubuws, 0, 26),
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GEN_VXFORM(vsubsbs, 0, 28),
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GEN_VXFORM(vsubshs, 0, 29),
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