nvic: Add cached vectpending_is_s_banked state

With banked exceptions, just the exception number in
s->vectpending is no longer sufficient to uniquely identify
the pending exception. Add a vectpending_is_s_banked bool
which is true if the exception is using the sec_vectors[]
array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-09-12 19:13:50 +01:00
parent 17906a162a
commit e93bc2ac11
2 changed files with 10 additions and 2 deletions

View File

@ -1254,6 +1254,7 @@ static void armv7m_nvic_reset(DeviceState *dev)
s->exception_prio = NVIC_NOEXC_PRIO;
s->vectpending = 0;
s->vectpending_is_s_banked = false;
}
static void nvic_systick_trigger(void *opaque, int n, int level)

View File

@ -57,10 +57,17 @@ typedef struct NVICState {
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
uint32_t prigroup;
/* vectpending and exception_prio are both cached state that can
* be recalculated from the vectors[] array and the prigroup field.
/* The following fields are all cached state that can be recalculated
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
* - vectpending
* - vectpending_is_secure
* - exception_prio
*/
unsigned int vectpending; /* highest prio pending enabled exception */
/* true if vectpending is a banked secure exception, ie it is in
* sec_vectors[] rather than vectors[]
*/
bool vectpending_is_s_banked;
int exception_prio; /* group prio of the highest prio active exception */
MemoryRegion sysregmem;