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Improve PPC device debugging

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6126 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-12-24 09:38:16 +00:00
parent 4017190e2d
commit ea026b2fc3
6 changed files with 90 additions and 36 deletions
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13
hw/adb.c
View File

@ -25,6 +25,16 @@
#include "ppc_mac.h" #include "ppc_mac.h"
#include "console.h" #include "console.h"
/* debug ADB */
//#define DEBUG_ADB
#ifdef DEBUG_ADB
#define ADB_DPRINTF(fmt, args...) \
do { printf("ADB: " fmt , ##args); } while (0)
#else
#define ADB_DPRINTF(fmt, args...)
#endif
/* ADB commands */ /* ADB commands */
#define ADB_BUSRESET 0x00 #define ADB_BUSRESET 0x00
#define ADB_FLUSH 0x01 #define ADB_FLUSH 0x01
@ -351,6 +361,7 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf,
olen = 0; olen = 0;
switch(cmd) { switch(cmd) {
case ADB_WRITEREG: case ADB_WRITEREG:
ADB_DPRINTF("write reg %d val 0x%2.2x\n", reg, buf[1]);
switch(reg) { switch(reg) {
case 2: case 2:
break; break;
@ -383,6 +394,8 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf,
olen = 2; olen = 2;
break; break;
} }
ADB_DPRINTF("read reg %d obuf[0] 0x%2.2x obuf[1] 0x%2.2x\n", reg,
obuf[0], obuf[1]);
break; break;
} }
return olen; return olen;

37
hw/cuda.c
View File

@ -29,9 +29,19 @@
/* XXX: implement all timer modes */ /* XXX: implement all timer modes */
/* debug CUDA */
//#define DEBUG_CUDA //#define DEBUG_CUDA
/* debug CUDA packets */
//#define DEBUG_CUDA_PACKET //#define DEBUG_CUDA_PACKET
#ifdef DEBUG_CUDA
#define CUDA_DPRINTF(fmt, args...) \
do { printf("CUDA: " fmt , ##args); } while (0)
#else
#define CUDA_DPRINTF(fmt, args...)
#endif
/* Bits in B data register: all active low */ /* Bits in B data register: all active low */
#define TREQ 0x08 /* Transfer request (input) */ #define TREQ 0x08 /* Transfer request (input) */
#define TACK 0x10 /* Transfer acknowledge (output) */ #define TACK 0x10 /* Transfer acknowledge (output) */
@ -176,10 +186,7 @@ static unsigned int get_counter(CUDATimer *s)
static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
{ {
#ifdef DEBUG_CUDA CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
printf("cuda: T%d.counter=%d\n",
1 + (ti->timer == NULL), val);
#endif
ti->load_time = qemu_get_clock(vm_clock); ti->load_time = qemu_get_clock(vm_clock);
ti->counter_value = val; ti->counter_value = val;
cuda_timer_update(s, ti, ti->load_time); cuda_timer_update(s, ti, ti->load_time);
@ -209,12 +216,8 @@ static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
} else { } else {
next_time = d + counter; next_time = d + counter;
} }
#if 0 CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
#ifdef DEBUG_CUDA
printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
s->latch, d, next_time - d); s->latch, d, next_time - d);
#endif
#endif
next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
s->load_time; s->load_time;
if (next_time <= current_time) if (next_time <= current_time)
@ -311,10 +314,8 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
val = s->anh; val = s->anh;
break; break;
} }
#ifdef DEBUG_CUDA
if (addr != 13 || val != 0) if (addr != 13 || val != 0)
printf("cuda: read: reg=0x%x val=%02x\n", addr, val); CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val);
#endif
return val; return val;
} }
@ -323,9 +324,7 @@ static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
CUDAState *s = opaque; CUDAState *s = opaque;
addr = (addr >> 9) & 0xf; addr = (addr >> 9) & 0xf;
#ifdef DEBUG_CUDA CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val);
printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
#endif
switch(addr) { switch(addr) {
case 0: case 0:
@ -412,9 +411,7 @@ static void cuda_update(CUDAState *s)
/* data output */ /* data output */
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
if (s->data_out_index < sizeof(s->data_out)) { if (s->data_out_index < sizeof(s->data_out)) {
#ifdef DEBUG_CUDA CUDA_DPRINTF("send: %02x\n", s->sr);
printf("cuda: send: %02x\n", s->sr);
#endif
s->data_out[s->data_out_index++] = s->sr; s->data_out[s->data_out_index++] = s->sr;
s->ifr |= SR_INT; s->ifr |= SR_INT;
cuda_update_irq(s); cuda_update_irq(s);
@ -425,9 +422,7 @@ static void cuda_update(CUDAState *s)
/* data input */ /* data input */
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
s->sr = s->data_in[s->data_in_index++]; s->sr = s->data_in[s->data_in_index++];
#ifdef DEBUG_CUDA CUDA_DPRINTF("recv: %02x\n", s->sr);
printf("cuda: recv: %02x\n", s->sr);
#endif
/* indicate end of transfer */ /* indicate end of transfer */
if (s->data_in_index >= s->data_in_size) { if (s->data_in_index >= s->data_in_size) {
s->b = (s->b | TREQ); s->b = (s->b | TREQ);

16
hw/grackle_pci.c
View File

@ -27,6 +27,16 @@
#include "ppc_mac.h" #include "ppc_mac.h"
#include "pci.h" #include "pci.h"
/* debug Grackle */
//#define DEBUG_GRACKLE
#ifdef DEBUG_GRACKLE
#define GRACKLE_DPRINTF(fmt, args...) \
do { printf("GRACKLE: " fmt , ##args); } while (0)
#else
#define GRACKLE_DPRINTF(fmt, args...)
#endif
typedef target_phys_addr_t pci_addr_t; typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h" #include "pci_host.h"
@ -36,6 +46,9 @@ static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val) uint32_t val)
{ {
GrackleState *s = opaque; GrackleState *s = opaque;
GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
val);
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val); val = bswap32(val);
#endif #endif
@ -51,6 +64,8 @@ static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val); val = bswap32(val);
#endif #endif
GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
val);
return val; return val;
} }
@ -86,6 +101,7 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
{ {
GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
qemu_set_irq(pic[irq_num + 0x15], level); qemu_set_irq(pic[irq_num + 0x15], level);
} }

20
hw/heathrow_pic.c
View File

@ -25,7 +25,15 @@
#include "hw.h" #include "hw.h"
#include "ppc_mac.h" #include "ppc_mac.h"
//#define DEBUG /* debug PIC */
//#define DEBUG_PIC
#ifdef DEBUG_PIC
#define PIC_DPRINTF(fmt, args...) \
do { printf("PIC: " fmt , ##args); } while (0)
#else
#define PIC_DPRINTF(fmt, args...)
#endif
typedef struct HeathrowPIC { typedef struct HeathrowPIC {
uint32_t events; uint32_t events;
@ -64,9 +72,7 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
value = bswap32(value); value = bswap32(value);
#endif #endif
n = ((addr & 0xfff) - 0x10) >> 4; n = ((addr & 0xfff) - 0x10) >> 4;
#ifdef DEBUG PIC_DPRINTF("writel: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
printf("pic_writel: " PADDRX " %u: %08x\n", addr, n, value);
#endif
if (n >= 2) if (n >= 2)
return; return;
pic = &s->pics[n]; pic = &s->pics[n];
@ -113,9 +119,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
break; break;
} }
} }
#ifdef DEBUG PIC_DPRINTF("readl: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
printf("pic_readl: " PADDRX " %u: %08x\n", addr, n, value);
#endif
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value); value = bswap32(value);
#endif #endif
@ -145,7 +149,7 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level)
{ {
static int last_level[64]; static int last_level[64];
if (last_level[num] != level) { if (last_level[num] != level) {
printf("set_irq: num=0x%02x level=%d\n", num, level); PIC_DPRINTF("set_irq: num=0x%02x level=%d\n", num, level);
last_level[num] = level; last_level[num] = level;
} }
} }

20
hw/mac_dbdma.c
View File

@ -25,38 +25,54 @@
#include "hw.h" #include "hw.h"
#include "ppc_mac.h" #include "ppc_mac.h"
/* debug DBDMA */
//#define DEBUG_DBDMA
#ifdef DEBUG_DBDMA
#define DBDMA_DPRINTF(fmt, args...) \
do { printf("DBDMA: " fmt , ##args); } while (0)
#else
#define DBDMA_DPRINTF(fmt, args...)
#endif
/* DBDMA: currently no op - should suffice right now */ /* DBDMA: currently no op - should suffice right now */
static void dbdma_writeb (void *opaque, static void dbdma_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value) target_phys_addr_t addr, uint32_t value)
{ {
printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value); DBDMA_DPRINTF("writeb 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
} }
static void dbdma_writew (void *opaque, static void dbdma_writew (void *opaque,
target_phys_addr_t addr, uint32_t value) target_phys_addr_t addr, uint32_t value)
{ {
DBDMA_DPRINTF("writew 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
} }
static void dbdma_writel (void *opaque, static void dbdma_writel (void *opaque,
target_phys_addr_t addr, uint32_t value) target_phys_addr_t addr, uint32_t value)
{ {
DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
} }
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
{ {
printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr); DBDMA_DPRINTF("readb 0x" TARGET_FMT_plx " => 0\n", addr);
return 0; return 0;
} }
static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
{ {
DBDMA_DPRINTF("readw 0x" TARGET_FMT_plx " => 0\n", addr);
return 0; return 0;
} }
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
{ {
DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0\n", addr);
return 0; return 0;
} }

18
hw/mac_nvram.c
View File

@ -25,6 +25,16 @@
#include "hw.h" #include "hw.h"
#include "ppc_mac.h" #include "ppc_mac.h"
/* debug NVR */
//#define DEBUG_NVR
#ifdef DEBUG_NVR
#define NVR_DPRINTF(fmt, args...) \
do { printf("NVR: " fmt , ##args); } while (0)
#else
#define NVR_DPRINTF(fmt, args...)
#endif
struct MacIONVRAMState { struct MacIONVRAMState {
target_phys_addr_t size; target_phys_addr_t size;
int mem_index; int mem_index;
@ -37,11 +47,11 @@ uint32_t macio_nvram_read (void *opaque, uint32_t addr)
MacIONVRAMState *s = opaque; MacIONVRAMState *s = opaque;
uint32_t ret; uint32_t ret;
// printf("%s: %p addr %04x\n", __func__, s, addr);
if (addr < 0x2000) if (addr < 0x2000)
ret = s->data[addr]; ret = s->data[addr];
else else
ret = -1; ret = -1;
NVR_DPRINTF("read addr %04x val %x\n", addr, ret);
return ret; return ret;
} }
@ -50,7 +60,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
{ {
MacIONVRAMState *s = opaque; MacIONVRAMState *s = opaque;
// printf("%s: %p addr %04x val %02x\n", __func__, s, addr, val); NVR_DPRINTF("write addr %04x val %x\n", addr, val);
if (addr < 0x2000) if (addr < 0x2000)
s->data[addr] = val; s->data[addr] = val;
} }
@ -63,7 +73,7 @@ static void macio_nvram_writeb (void *opaque,
addr = (addr >> 4) & 0x1fff; addr = (addr >> 4) & 0x1fff;
s->data[addr] = value; s->data[addr] = value;
// printf("macio_nvram_writeb %04x = %02x\n", addr, value); NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
} }
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
@ -73,7 +83,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
addr = (addr >> 4) & 0x1fff; addr = (addr >> 4) & 0x1fff;
value = s->data[addr]; value = s->data[addr];
// printf("macio_nvram_readb %04x = %02x\n", addr, value); NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value);
return value; return value;
} }