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tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec

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This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-09-14 20:44:53 -07:00
parent 9bca986df8
commit ea3f2af8f1
1 changed files with 23 additions and 1 deletions
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24
tcg/s390x/tcg-target.c.inc
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@ -2869,6 +2869,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_xor_vec:
return 1;
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
case INDEX_op_rotrv_vec:
return -1;
case INDEX_op_mul_vec:
@ -2931,6 +2932,21 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
}
}
static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec c1, TCGv_vec c2,
TCGv_vec v3, TCGv_vec v4, TCGCond cond)
{
TCGv_vec t = tcg_temp_new_vec(type);
if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) {
/* Invert the sense of the compare by swapping arguments. */
tcg_gen_bitsel_vec(vece, v0, t, v4, v3);
} else {
tcg_gen_bitsel_vec(vece, v0, t, v3, v4);
}
tcg_temp_free_vec(t);
}
static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc)
{
@ -2972,7 +2988,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
va_list va;
TCGv_vec v0, v1, v2, t0;
TCGv_vec v0, v1, v2, v3, v4, t0;
va_start(va, a0);
v0 = temp_tcgv_vec(arg_temp(a0));
@ -2984,6 +3000,12 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
break;
case INDEX_op_cmpsel_vec:
v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg));
break;
case INDEX_op_rotrv_vec:
t0 = tcg_temp_new_vec(type);
tcg_gen_neg_vec(vece, t0, v2);