target-arm queue:
* target/arm: Fix some bugs in secure EL2 handling * target/arm: Fix assert when !HAVE_CMPXCHG128 * MAINTAINERS: change Fred Konrad's email address -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJHE28ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3izND/0RuCk7xsg/X4QVk0yeHi6T AavOkb2a5Jo3wqW4z4FLWC0C+0nq+SYI7/sR9UgDWBCGYQH+c+5vYdpxLb222Xxf lT63f2Gb84RtKddmJ96giy4gBVyXPZHKfBLb64EavP870wIOCkkOLabfQz8qgkzB e+dDZVcboLq0XLKQkQ1p6CgaJZ2KWJ884qllzk1yRdh3oMJf6uhXN3bH0QDZav1C 4qUcZxsE53U4DNGC19I6sXh+bBpwLv0qGVCVTZ0lbtOd6tIeCtmsf3QpooOoki9g kuI3Ty5gALxU1FVItnYVDUFJpRrIUAFKIhRKkXZBDhKnrRqANzqj9NWz/4DWSHXA uNX1WOmN/Lgk4NVdPGe/QLIbY8HtweZG2KWZ4ktJz7l12A8XYRhslD7StCvdmJrq FYqUp8T1/l/+ZgTuWkLcNzepSNw02vWpZJre3VnulDR0dLPdh0f9NhPn3D7ITqv2 MeYA6eorC6oNn525oE0oFaJMVuyoGteeSMC+gZlFb7uwqpWATynR+fxF2EB9ZsI6 4pY7gNseZn7q6lBGf/2CNTEmxACe8OMRShZOfrqVR2G6c+SYQxSJal/lk7NmcEMp MMSxxWn7pcRnqliZxFXz+PukWmZ93+xUhHXW/Mq+ImslW8NqdgC6mc/0Enj2sCSL jsL4wB9r0QcX2jNS74ZiJw== =WcCR -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * target/arm: Fix some bugs in secure EL2 handling * target/arm: Fix assert when !HAVE_CMPXCHG128 * MAINTAINERS: change Fred Konrad's email address # gpg: Signature made Fri 01 Apr 2022 15:59:59 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen MAINTAINERS: change Fred Konrad's email address target/arm: Determine final stage 2 output PA space based on original IPA target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk target/arm: Check VSTCR.SW when assigning the stage 2 output PA space target/arm: Fix MTE access checks for disabled SEL2 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
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@ -56,7 +56,8 @@ Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
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Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
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Christian Borntraeger <borntraeger@linux.ibm.com> <borntraeger@de.ibm.com>
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Filip Bozuta <filip.bozuta@syrmia.com> <filip.bozuta@rt-rk.com.com>
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Frederic Konrad <konrad@adacore.com> <fred.konrad@greensocs.com>
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Frederic Konrad <konrad.frederic@yahoo.fr> <fred.konrad@greensocs.com>
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Frederic Konrad <konrad.frederic@yahoo.fr> <konrad@adacore.com>
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Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
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Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
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Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
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@ -1533,7 +1533,7 @@ F: include/hw/rtc/sun4v-rtc.h
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Leon3
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M: Fabien Chouteau <chouteau@adacore.com>
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M: KONRAD Frederic <frederic.konrad@adacore.com>
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M: Frederic Konrad <konrad.frederic@yahoo.fr>
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S: Maintained
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F: hw/sparc/leon3.c
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F: hw/*/grlib*
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@ -7176,7 +7176,7 @@ static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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int el = arm_current_el(env);
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if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
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if (el < 2 && arm_is_el2_enabled(env)) {
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uint64_t hcr = arm_hcr_el2_eff(env);
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if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
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return CP_ACCESS_TRAP_EL2;
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@ -12644,6 +12644,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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hwaddr ipa;
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int s2_prot;
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int ret;
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bool ipa_secure;
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ARMCacheAttrs cacheattrs2 = {};
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ARMMMUIdx s2_mmu_idx;
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bool is_el0;
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@ -12657,6 +12658,17 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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return ret;
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}
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ipa_secure = attrs->secure;
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if (arm_is_secure_below_el3(env)) {
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if (ipa_secure) {
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attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
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} else {
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attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
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}
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} else {
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assert(!ipa_secure);
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}
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s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
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is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
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@ -12691,13 +12703,13 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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/* Check if IPA translates to secure or non-secure PA space. */
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if (arm_is_secure_below_el3(env)) {
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if (attrs->secure) {
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if (ipa_secure) {
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attrs->secure =
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!(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW));
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} else {
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attrs->secure =
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!((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW))
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|| (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA));
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|| (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)));
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}
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}
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return 0;
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@ -1094,7 +1094,7 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
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&& !(env->cp15.scr_el3 & SCR_ATA)) {
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return false;
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}
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if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
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if (el < 2 && arm_is_el2_enabled(env)) {
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uint64_t hcr = arm_hcr_el2_eff(env);
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if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
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return false;
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@ -2470,7 +2470,12 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
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if (!HAVE_CMPXCHG128) {
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gen_helper_exit_atomic(cpu_env);
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s->base.is_jmp = DISAS_NORETURN;
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/*
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* Produce a result so we have a well-formed opcode
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* stream when the following (dead) code uses 'tmp'.
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* TCG will remove the dead ops for us.
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*/
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tcg_gen_movi_i64(tmp, 0);
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} else if (s->be_data == MO_LE) {
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gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env,
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cpu_exclusive_addr,
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