target/mips: Move comment containing summary of CP0 registers
Move comment containing summary of CP0 registers. Checkpatch script reported some tabs in the resutling diff, so convert these tabs to spaces too. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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Aleksandar Markovic
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@ -123,87 +123,6 @@ typedef struct mips_def_t mips_def_t;
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#define MIPS_KSCRATCH_NUM 6
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#define MIPS_MAAR_MAX 16 /* Must be an even number. */
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typedef struct TCState TCState;
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struct TCState {
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target_ulong gpr[32];
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target_ulong PC;
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target_ulong HI[MIPS_DSP_ACC];
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target_ulong LO[MIPS_DSP_ACC];
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target_ulong ACX[MIPS_DSP_ACC];
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target_ulong DSPControl;
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int32_t CP0_TCStatus;
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#define CP0TCSt_TCU3 31
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#define CP0TCSt_TCU2 30
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#define CP0TCSt_TCU1 29
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#define CP0TCSt_TCU0 28
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#define CP0TCSt_TMX 27
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#define CP0TCSt_RNST 23
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#define CP0TCSt_TDS 21
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#define CP0TCSt_DT 20
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#define CP0TCSt_DA 15
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#define CP0TCSt_A 13
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#define CP0TCSt_TKSU 11
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#define CP0TCSt_IXMT 10
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#define CP0TCSt_TASID 0
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int32_t CP0_TCBind;
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#define CP0TCBd_CurTC 21
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#define CP0TCBd_TBE 17
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#define CP0TCBd_CurVPE 0
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target_ulong CP0_TCHalt;
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target_ulong CP0_TCContext;
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target_ulong CP0_TCSchedule;
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target_ulong CP0_TCScheFBack;
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int32_t CP0_Debug_tcstatus;
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target_ulong CP0_UserLocal;
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int32_t msacsr;
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#define MSACSR_FS 24
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#define MSACSR_FS_MASK (1 << MSACSR_FS)
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#define MSACSR_NX 18
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#define MSACSR_NX_MASK (1 << MSACSR_NX)
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#define MSACSR_CEF 2
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#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
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#define MSACSR_RM 0
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#define MSACSR_RM_MASK (0x3 << MSACSR_RM)
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#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
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MSACSR_FS_MASK)
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float_status msa_fp_status;
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#define NUMBER_OF_MXU_REGISTERS 16
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target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
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target_ulong mxu_cr;
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#define MXU_CR_LC 31
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#define MXU_CR_RC 30
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#define MXU_CR_BIAS 2
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#define MXU_CR_RD_EN 1
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#define MXU_CR_MXU_EN 0
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};
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typedef struct CPUMIPSState CPUMIPSState;
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struct CPUMIPSState {
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TCState active_tc;
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CPUMIPSFPUContext active_fpu;
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uint32_t current_tc;
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uint32_t current_fpu;
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uint32_t SEGBITS;
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uint32_t PABITS;
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#if defined(TARGET_MIPS64)
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# define PABITS_BASE 36
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#else
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# define PABITS_BASE 32
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#endif
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target_ulong SEGMask;
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uint64_t PAMask;
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#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
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int32_t msair;
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#define MSAIR_ProcID 8
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#define MSAIR_Rev 0
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/*
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* Summary of CP0 registers
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@ -314,6 +233,90 @@ struct CPUMIPSState {
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* 7 TagLo TagHi KScratch<n>
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*
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*/
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typedef struct TCState TCState;
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struct TCState {
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target_ulong gpr[32];
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target_ulong PC;
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target_ulong HI[MIPS_DSP_ACC];
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target_ulong LO[MIPS_DSP_ACC];
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target_ulong ACX[MIPS_DSP_ACC];
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target_ulong DSPControl;
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int32_t CP0_TCStatus;
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#define CP0TCSt_TCU3 31
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#define CP0TCSt_TCU2 30
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#define CP0TCSt_TCU1 29
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#define CP0TCSt_TCU0 28
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#define CP0TCSt_TMX 27
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#define CP0TCSt_RNST 23
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#define CP0TCSt_TDS 21
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#define CP0TCSt_DT 20
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#define CP0TCSt_DA 15
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#define CP0TCSt_A 13
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#define CP0TCSt_TKSU 11
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#define CP0TCSt_IXMT 10
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#define CP0TCSt_TASID 0
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int32_t CP0_TCBind;
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#define CP0TCBd_CurTC 21
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#define CP0TCBd_TBE 17
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#define CP0TCBd_CurVPE 0
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target_ulong CP0_TCHalt;
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target_ulong CP0_TCContext;
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target_ulong CP0_TCSchedule;
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target_ulong CP0_TCScheFBack;
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int32_t CP0_Debug_tcstatus;
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target_ulong CP0_UserLocal;
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int32_t msacsr;
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#define MSACSR_FS 24
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#define MSACSR_FS_MASK (1 << MSACSR_FS)
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#define MSACSR_NX 18
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#define MSACSR_NX_MASK (1 << MSACSR_NX)
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#define MSACSR_CEF 2
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#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
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#define MSACSR_RM 0
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#define MSACSR_RM_MASK (0x3 << MSACSR_RM)
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#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
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MSACSR_FS_MASK)
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float_status msa_fp_status;
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#define NUMBER_OF_MXU_REGISTERS 16
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target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
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target_ulong mxu_cr;
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#define MXU_CR_LC 31
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#define MXU_CR_RC 30
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#define MXU_CR_BIAS 2
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#define MXU_CR_RD_EN 1
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#define MXU_CR_MXU_EN 0
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};
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typedef struct CPUMIPSState CPUMIPSState;
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struct CPUMIPSState {
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TCState active_tc;
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CPUMIPSFPUContext active_fpu;
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uint32_t current_tc;
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uint32_t current_fpu;
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uint32_t SEGBITS;
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uint32_t PABITS;
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#if defined(TARGET_MIPS64)
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# define PABITS_BASE 36
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#else
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# define PABITS_BASE 32
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#endif
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target_ulong SEGMask;
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uint64_t PAMask;
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#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
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int32_t msair;
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#define MSAIR_ProcID 8
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#define MSAIR_Rev 0
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/*
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* CP0 Register 0
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*/
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