Implement PowerPC 64 SLB invalidation helpers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3391 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -601,6 +601,16 @@ static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
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}
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#if defined(TARGET_PPC64)
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static inline int slb_is_valid (uint64_t slb64)
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{
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return slb64 & 0x0000000008000000ULL ? 1 : 0;
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}
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static inline void slb_invalidate (uint64_t *slb64)
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{
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*slb64 &= ~0x0000000008000000ULL;
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}
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static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
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target_ulong *vsid, target_ulong *page_mask, int *attr)
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{
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@ -609,7 +619,6 @@ static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
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uint64_t tmp64;
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uint32_t tmp;
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int n, ret;
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int slb_nr;
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ret = -5;
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sr_base = env->spr[SPR_ASR];
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@ -620,8 +629,7 @@ static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
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}
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#endif
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mask = 0x0000000000000000ULL; /* Avoid gcc warning */
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slb_nr = env->slb_nr;
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for (n = 0; n < slb_nr; n++) {
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for (n = 0; n < env->slb_nr; n++) {
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tmp64 = ldq_phys(sr_base);
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tmp = ldl_phys(sr_base + 8);
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#if defined(DEBUG_SLB)
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@ -630,7 +638,7 @@ static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
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PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
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}
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#endif
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if (tmp64 & 0x0000000008000000ULL) {
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if (slb_is_valid(tmp64)) {
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/* SLB entry is valid */
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switch (tmp64 & 0x0000000006000000ULL) {
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case 0x0000000000000000ULL:
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@ -651,7 +659,7 @@ static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
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*vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
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*page_mask = ~mask;
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*attr = tmp & 0xFF;
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ret = 0;
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ret = n;
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break;
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}
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}
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@ -661,6 +669,56 @@ static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
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return ret;
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}
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void ppc_slb_invalidate_all (CPUPPCState *env)
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{
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target_phys_addr_t sr_base;
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uint64_t tmp64;
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int n, do_invalidate;
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do_invalidate = 0;
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sr_base = env->spr[SPR_ASR];
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for (n = 0; n < env->slb_nr; n++) {
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tmp64 = ldq_phys(sr_base);
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if (slb_is_valid(tmp64)) {
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slb_invalidate(&tmp64);
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stq_phys(sr_base, tmp64);
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/* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in Qemu, we just invalidate all TLBs
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*/
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do_invalidate = 1;
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}
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sr_base += 12;
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}
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if (do_invalidate)
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tlb_flush(env, 1);
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}
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void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
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{
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target_phys_addr_t sr_base;
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target_ulong vsid, page_mask;
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uint64_t tmp64;
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int attr;
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int n;
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n = slb_lookup(env, T0, &vsid, &page_mask, &attr);
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if (n >= 0) {
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sr_base = env->spr[SPR_ASR];
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sr_base += 12 * n;
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tmp64 = ldq_phys(sr_base);
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if (slb_is_valid(tmp64)) {
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slb_invalidate(&tmp64);
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stq_phys(sr_base, tmp64);
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/* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in Qemu, we just invalidate all TLBs
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*/
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tlb_flush(env, 1);
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}
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}
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}
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target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
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{
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target_phys_addr_t sr_base;
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@ -1828,20 +1886,6 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
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#endif
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}
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#if defined(TARGET_PPC64)
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void ppc_slb_invalidate_all (CPUPPCState *env)
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{
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/* XXX: TODO */
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tlb_flush(env, 1);
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}
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void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
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{
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/* XXX: TODO */
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tlb_flush(env, 1);
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}
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#endif
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/*****************************************************************************/
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/* Special registers manipulation */
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#if defined(TARGET_PPC64)
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