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tests/tcg/hexagon: fix underspecifed asm constraints

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There are two test cases where the inline asm doesn't
have the correct constraints causing them to fail.

In misc.c, the 'result' output needs the early clobber
modifier since the rest of the inputs are read after
assignment to the output register.

In mem_noshuf.c, the register r7 is written to but
not specified in the clobber list.

Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20221229081836.12130-1-quic_mthiyaga@quicinc.com>
This commit is contained in:
Mukilan Thiyagarajan 2022-12-29 13:48:36 +05:30 committed by Taylor Simpson
parent 72895676e7
commit eaee3b6faf
2 changed files with 4 additions and 4 deletions
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2
tests/tcg/hexagon/mem_noshuf.c
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@ -144,7 +144,7 @@ static inline long long pred_ld_sd_pi(int pred, long long *p, long long *q,
"}:mem_noshuf\n"
: "=&r"(ret)
: "r"(p), "r"(q), "r"(x), "r"(y), "r"(pred)
: "p0", "memory");
: "r7", "p0", "memory");
return ret;
}

6
tests/tcg/hexagon/misc.c
View File

@ -186,10 +186,10 @@ static int L2_ploadrifnew_pi(void *p, int pred)
int result;
asm volatile("%0 = #31\n\t"
"{\n\t"
" p0 = cmp.eq(%1, #1)\n\t"
" if (!p0.new) %0 = memw(%2++#4)\n\t"
" p0 = cmp.eq(%2, #1)\n\t"
" if (!p0.new) %0 = memw(%1++#4)\n\t"
"}\n\t"
: "=r"(result) : "r"(pred), "r"(p)
: "=&r"(result), "+r"(p) : "r"(pred)
: "p0");
return result;
}