From eb3f4298c96d79a5a67b904c28f293864cc5ccc3 Mon Sep 17 00:00:00 2001
From: Max Filippov <jcmvbkbc@gmail.com>
Date: Mon, 18 Feb 2019 03:11:40 -0800
Subject: [PATCH] target/xtensa: implement PREFCTL SR

Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target/xtensa/cpu.h       |  1 +
 target/xtensa/translate.c | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index a01a94e2a6..4d8152682f 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -131,6 +131,7 @@ enum {
     ACCLO = 16,
     ACCHI = 17,
     MR = 32,
+    PREFCTL = 40,
     WINDOW_BASE = 72,
     WINDOW_START = 73,
     PTEVADDR = 83,
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 338e6ca70f..77bc04d6b0 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -134,6 +134,7 @@ static const XtensaReg sregnames[256] = {
     [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
     [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
     [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
+    [PREFCTL] = XTENSA_REG_BITS("PREFCTL", XTENSA_OPTION_ALL),
     [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
     [WINDOW_START] = XTENSA_REG("WINDOW_START",
             XTENSA_OPTION_WINDOWED_REGISTER),
@@ -4152,6 +4153,11 @@ static const XtensaOpcodeOps core_ops[] = {
         .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MISC + 3},
         .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "rsr.prefctl",
+        .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
+        .par = (const uint32_t[]){PREFCTL},
     }, {
         .name = "rsr.prid",
         .translate = translate_rsr,
@@ -4777,6 +4783,11 @@ static const XtensaOpcodeOps core_ops[] = {
         .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MMID},
         .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "wsr.prefctl",
+        .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
+        .par = (const uint32_t[]){PREFCTL},
     }, {
         .name = "wsr.prid",
         .translate = translate_wsr,
@@ -5265,6 +5276,11 @@ static const XtensaOpcodeOps core_ops[] = {
         .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MISC + 3},
         .op_flags = XTENSA_OP_PRIVILEGED,
+    }, {
+        .name = "xsr.prefctl",
+        .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
+        .par = (const uint32_t[]){PREFCTL},
     }, {
         .name = "xsr.prid",
         .translate = translate_xsr,