target/mips: Introduce MXU registers

Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Craig Janeczek 2018-10-18 14:06:20 +02:00 committed by Aleksandar Markovic
parent 2431a422d3
commit eb5559f67d
2 changed files with 30 additions and 0 deletions

View File

@ -170,6 +170,16 @@ struct TCState {
MSACSR_FS_MASK)
float_status msa_fp_status;
#define NUMBER_OF_MXU_REGISTERS 16
target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
target_ulong mxu_cr;
#define MXU_CR_LC 31
#define MXU_CR_RC 30
#define MXU_CR_BIAS 2
#define MXU_CR_RD_EN 1
#define MXU_CR_MXU_EN 0
};
typedef struct CPUMIPSState CPUMIPSState;

View File

@ -2379,6 +2379,10 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
static TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
/* MXU registers */
static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
static TCGv mxu_CR;
#include "exec/gen-icount.h"
#define gen_helper_0e0i(name, arg) do { \
@ -2501,6 +2505,11 @@ static const char * const msaregnames[] = {
"w30.d0", "w30.d1", "w31.d0", "w31.d1",
};
static const char * const mxuregnames[] = {
"XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
"XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
};
#define LOG_DISAS(...) \
do { \
if (MIPS_DEBUG_DISAS) { \
@ -27231,6 +27240,17 @@ void mips_tcg_init(void)
fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
mxu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState,
active_tc.mxu_gpr[i]),
mxuregnames[i]);
}
mxu_CR = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.mxu_cr),
mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
}
#include "translate_init.inc.c"