OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper

Browse Source 
fsel doesn't change FPSCR and CR1 is handled by gen_set_cr1_from_fpscr,
so helper_fsel doesn't need the env argument and can be declared with
TCG_CALL_NO_RWG_SE. We also take this opportunity to move the insn to
decodetree.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Matheus Ferst 2022-05-17 09:39:22 -03:00 committed by Daniel Henrique Barboza
parent f2454bfe73
commit eb69a84bb0
5 changed files with 43 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
target/ppc/fpu_helper.c
View File

@ -919,18 +919,17 @@ float64 helper_frsqrtes(CPUPPCState *env, float64 arg)
}
/* fsel - fsel. */
uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
uint64_t arg3)
uint64_t helper_FSEL(uint64_t a, uint64_t b, uint64_t c)
{
CPU_DoubleU farg1;
CPU_DoubleU fa;
farg1.ll = arg1;
fa.ll = a;
if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
!float64_is_any_nan(farg1.d)) {
return arg2;
if ((!float64_is_neg(fa.d) || float64_is_zero(fa.d)) &&
!float64_is_any_nan(fa.d)) {
return c;
} else {
return arg3;
return b;
}
}

2
target/ppc/helper.h
View File

@ -120,7 +120,7 @@ DEF_HELPER_2(fre, i64, env, i64)
DEF_HELPER_2(fres, i64, env, i64)
DEF_HELPER_2(frsqrte, i64, env, i64)
DEF_HELPER_2(frsqrtes, i64, env, i64)
DEF_HELPER_4(fsel, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_3(FSEL, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(ftdiv, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)

7
target/ppc/insn32.decode
View File

@ -17,6 +17,9 @@
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
&A frt fra frb frc rc:bool
@A ...... frt:5 fra:5 frb:5 frc:5 ..... rc:1 &A
&D rt ra si:int64_t
@D ...... rt:5 ra:5 si:s16 &D
@ -308,6 +311,10 @@ STFDU 110111 ..... ...... ............... @D
STFDX 011111 ..... ...... .... 1011010111 - @X
STFDUX 011111 ..... ...... .... 1011110111 - @X
### Floating-Point Select Instruction
FSEL 111111 ..... ..... ..... ..... 10111 . @A
### Move To/From System Register Instructions
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi

30
target/ppc/translate/fp-impl.c.inc
View File

@ -222,8 +222,34 @@ static void gen_frsqrtes(DisasContext *ctx)
tcg_temp_free_i64(t1);
}
/* fsel */
_GEN_FLOAT_ACB(sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL);
static bool trans_FSEL(DisasContext *ctx, arg_A *a)
{
TCGv_i64 t0, t1, t2;
REQUIRE_INSNS_FLAGS(ctx, FLOAT_FSEL);
REQUIRE_FPU(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
get_fpr(t0, a->fra);
get_fpr(t1, a->frb);
get_fpr(t2, a->frc);
gen_helper_FSEL(t0, t0, t1, t2);
set_fpr(a->frt, t0);
if (a->rc) {
gen_set_cr1_from_fpscr(ctx);
}
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
return true;
}
/* fsub - fsubs */
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
/* Optional: */

1
target/ppc/translate/fp-ops.c.inc
View File

@ -24,7 +24,6 @@ GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),