hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state
Now that the GIC base class has state fields for the GICD_IGROUPRn registers, make kvm_arm_gic_get() and kvm_arm_gic_put() write and read them. This allows us to remove the check that made us fail migration if the guest had set any of the group register bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-6-git-send-email-peter.maydell@linaro.org
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@ -176,6 +176,20 @@ static void translate_clear(GICState *s, int irq, int cpu,
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}
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}
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static void translate_group(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
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if (to_kernel) {
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*field = GIC_TEST_GROUP(irq, cm);
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} else {
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if (*field & 1) {
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GIC_SET_GROUP(irq, cm);
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}
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}
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}
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static void translate_enabled(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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@ -365,6 +379,9 @@ static void kvm_arm_gic_put(GICState *s)
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kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
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kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);
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/* irq_state[n].group -> GICD_IGROUPRn */
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kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group);
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/* s->irq_target[irq] -> GICD_ITARGETSRn
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* (restore targets before pending to ensure the pending state is set on
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* the appropriate CPU interfaces in the kernel) */
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@ -454,21 +471,14 @@ static void kvm_arm_gic_get(GICState *s)
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/* GICD_IIDR -> ? */
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kvm_gicd_access(s, 0x8, 0, ®, false);
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/* Verify no GROUP 1 interrupts configured in the kernel */
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for_each_irq_reg(i, s->num_irq, 1) {
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kvm_gicd_access(s, 0x80 + (i * 4), 0, ®, false);
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if (reg != 0) {
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fprintf(stderr, "Unsupported GICD_IGROUPRn value: %08x\n",
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reg);
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abort();
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}
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}
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/* Clear all the IRQ settings */
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for (i = 0; i < s->num_irq; i++) {
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memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
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}
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/* GICD_IGROUPRn -> irq_state[n].group */
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kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group);
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/* GICD_ISENABLERn -> irq_state[n].enabled */
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kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);
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