target-tricore: Add instructions of RRRW opcode format
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -7636,6 +7636,65 @@ static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
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tcg_temp_free(tmp_width);
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}
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/* RRRW format */
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static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
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{
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uint32_t op2;
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int r1, r2, r3, r4;
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int32_t width;
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TCGv temp, temp2;
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op2 = MASK_OP_RRRW_OP2(ctx->opcode);
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r1 = MASK_OP_RRRW_S1(ctx->opcode);
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r2 = MASK_OP_RRRW_S2(ctx->opcode);
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r3 = MASK_OP_RRRW_S3(ctx->opcode);
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r4 = MASK_OP_RRRW_D(ctx->opcode);
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width = MASK_OP_RRRW_WIDTH(ctx->opcode);
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temp = tcg_temp_new();
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switch (op2) {
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case OPC2_32_RRRW_EXTR:
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tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
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tcg_gen_addi_tl(temp, temp, width);
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tcg_gen_subfi_tl(temp, 32, temp);
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tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
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tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
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break;
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case OPC2_32_RRRW_EXTR_U:
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if (width == 0) {
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tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
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} else {
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tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
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tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
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tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
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}
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break;
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case OPC2_32_RRRW_IMASK:
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temp2 = tcg_temp_new();
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tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
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tcg_gen_movi_tl(temp2, (1 << width) - 1);
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tcg_gen_shl_tl(temp2, temp2, temp);
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tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
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tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
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tcg_temp_free(temp2);
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break;
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case OPC2_32_RRRW_INSERT:
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temp2 = tcg_temp_new();
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tcg_gen_movi_tl(temp, width);
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tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
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gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
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tcg_temp_free(temp2);
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break;
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}
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tcg_temp_free(temp);
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}
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static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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{
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int op1;
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@ -7954,6 +8013,10 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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/* RRRR format */
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case OPCM_32_RRRR_EXTRACT_INSERT:
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decode_rrrr_extract_insert(env, ctx);
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/* RRRW format */
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case OPCM_32_RRRW_EXTRACT_INSERT:
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decode_rrrw_extract_insert(env, ctx);
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break;
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}
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}
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