target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX
Perform one atomic 16-byte operation. The atomicity is required for the LDTXA instructions. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -2594,11 +2594,27 @@ static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
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return;
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case GET_ASI_DTWINX:
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assert(TARGET_LONG_BITS == 64);
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tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop);
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#ifdef TARGET_SPARC64
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{
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MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16;
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TCGv_i128 t = tcg_temp_new_i128();
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tcg_gen_qemu_ld_i128(t, addr, da->mem_idx, mop);
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/*
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* Note that LE twinx acts as if each 64-bit register result is
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* byte swapped. We perform one 128-bit LE load, so must swap
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* the order of the writebacks.
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*/
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if ((mop & MO_BSWAP) == MO_TE) {
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tcg_gen_extr_i128_i64(lo, hi, t);
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} else {
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tcg_gen_extr_i128_i64(hi, lo, t);
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}
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}
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break;
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#else
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g_assert_not_reached();
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#endif
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case GET_ASI_DIRECT:
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{
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@ -2663,11 +2679,27 @@ static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
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break;
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case GET_ASI_DTWINX:
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assert(TARGET_LONG_BITS == 64);
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tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop);
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#ifdef TARGET_SPARC64
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{
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MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16;
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TCGv_i128 t = tcg_temp_new_i128();
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/*
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* Note that LE twinx acts as if each 64-bit register result is
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* byte swapped. We perform one 128-bit LE store, so must swap
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* the order of the construction.
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*/
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if ((mop & MO_BSWAP) == MO_TE) {
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tcg_gen_concat_i64_i128(t, lo, hi);
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} else {
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tcg_gen_concat_i64_i128(t, hi, lo);
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}
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tcg_gen_qemu_st_i128(t, addr, da->mem_idx, mop);
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}
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break;
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#else
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g_assert_not_reached();
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#endif
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case GET_ASI_DIRECT:
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{
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