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target/riscv: Set pc_succ_insn for !rvc illegal insn 

Failure to set pc_succ_insn may result in a TB covering zero bytes,
which triggers an assert within the code generator.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org>
[ Changes by AF:
 - Add missing run-plugin-test-noc-% line
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2022-12-03 11:57:44 -06:00 committed by Alistair Francis
parent 4c48aad122
commit ec2918b467
4 changed files with 44 additions and 8 deletions
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12
target/riscv/translate.c
View File

@ -1096,14 +1096,10 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
ctx->virt_inst_excp = false; ctx->virt_inst_excp = false;
/* Check for compressed insn */ /* Check for compressed insn */
if (insn_len(opcode) == 2) { if (insn_len(opcode) == 2) {
if (!has_ext(ctx, RVC)) { ctx->opcode = opcode;
gen_exception_illegal(ctx); ctx->pc_succ_insn = ctx->base.pc_next + 2;
} else { if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
ctx->opcode = opcode; return;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (decode_insn16(ctx, opcode)) {
return;
}
} }
} else { } else {
uint32_t opcode32 = opcode; uint32_t opcode32 = opcode;

2
tests/tcg/Makefile.target
View File

@ -117,6 +117,8 @@ endif
%: %.c %: %.c
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
%: %.S
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
else else
# For softmmu targets we include a different Makefile fragement as the # For softmmu targets we include a different Makefile fragement as the
# build options for bare programs are usually pretty different. They # build options for bare programs are usually pretty different. They

6
tests/tcg/riscv64/Makefile.target
View File

@ -4,3 +4,9 @@
VPATH += $(SRC_PATH)/tests/tcg/riscv64 VPATH += $(SRC_PATH)/tests/tcg/riscv64
TESTS += test-div TESTS += test-div
TESTS += noexec TESTS += noexec
# Disable compressed instructions for test-noc
TESTS += test-noc
test-noc: LDFLAGS = -nostdlib -static
run-test-noc: QEMU_OPTS += -cpu rv64,c=false
run-plugin-test-noc-%: QEMU_OPTS += -cpu rv64,c=false

32
tests/tcg/riscv64/test-noc.S Normal file
View File

@ -0,0 +1,32 @@
#include <asm/unistd.h>
.text
.globl _start
_start:
.option norvc
li a0, 4 /* SIGILL */
la a1, sa
li a2, 0
li a3, 8
li a7, __NR_rt_sigaction
scall
.option rvc
li a0, 1
j exit
.option norvc
pass:
li a0, 0
exit:
li a7, __NR_exit
scall
.data
/* struct kernel_sigaction sa = { .sa_handler = pass }; */
.type sa, @object
.size sa, 32
sa:
.dword pass
.zero 24