target/riscv: Set pc_succ_insn for !rvc illegal insn
Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -1096,15 +1096,11 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
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ctx->virt_inst_excp = false;
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/* Check for compressed insn */
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if (insn_len(opcode) == 2) {
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if (!has_ext(ctx, RVC)) {
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gen_exception_illegal(ctx);
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} else {
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ctx->opcode = opcode;
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ctx->pc_succ_insn = ctx->base.pc_next + 2;
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if (decode_insn16(ctx, opcode)) {
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if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
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return;
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}
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}
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} else {
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uint32_t opcode32 = opcode;
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opcode32 = deposit32(opcode32, 16, 16,
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@ -117,6 +117,8 @@ endif
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%: %.c
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$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
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%: %.S
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$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
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else
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# For softmmu targets we include a different Makefile fragement as the
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# build options for bare programs are usually pretty different. They
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@ -4,3 +4,9 @@
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VPATH += $(SRC_PATH)/tests/tcg/riscv64
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TESTS += test-div
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TESTS += noexec
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# Disable compressed instructions for test-noc
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TESTS += test-noc
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test-noc: LDFLAGS = -nostdlib -static
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run-test-noc: QEMU_OPTS += -cpu rv64,c=false
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run-plugin-test-noc-%: QEMU_OPTS += -cpu rv64,c=false
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@ -0,0 +1,32 @@
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#include <asm/unistd.h>
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.text
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.globl _start
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_start:
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.option norvc
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li a0, 4 /* SIGILL */
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la a1, sa
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li a2, 0
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li a3, 8
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li a7, __NR_rt_sigaction
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scall
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.option rvc
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li a0, 1
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j exit
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.option norvc
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pass:
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li a0, 0
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exit:
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li a7, __NR_exit
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scall
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.data
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/* struct kernel_sigaction sa = { .sa_handler = pass }; */
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.type sa, @object
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.size sa, 32
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sa:
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.dword pass
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.zero 24
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