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exec.c: Drop TARGET_HAS_ICE define and checks

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The TARGET_HAS_ICE #define is intended to indicate whether a target-*
guest CPU implementation supports the breakpoint handling. However,
all our guest CPUs have that support (the only two which do not
define TARGET_HAS_ICE are unicore32 and openrisc, and in both those
cases the bp support is present and the lack of the #define is just
a bug). So remove the #define entirely: all new guest CPU support
should include breakpoint handling as part of the basic implementation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2015-01-20 15:19:32 +00:00
parent 83ecb22ba2
commit ec53b45bcd
17 changed files with 2 additions and 48 deletions
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16
exec.c
View File

@ -553,7 +553,6 @@ void cpu_exec_init(CPUArchState *env)
}
}
#if defined(TARGET_HAS_ICE)
#if defined(CONFIG_USER_ONLY)
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
@ -569,7 +568,6 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
}
}
#endif
#endif /* TARGET_HAS_ICE */
#if defined(CONFIG_USER_ONLY)
void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
@ -689,7 +687,6 @@ static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint)
{
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
bp = g_malloc(sizeof(*bp));
@ -710,15 +707,11 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
*breakpoint = bp;
}
return 0;
#else
return -ENOSYS;
#endif
}
/* Remove a specific breakpoint. */
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
@ -728,27 +721,21 @@ int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
}
}
return -ENOENT;
#else
return -ENOSYS;
#endif
}
/* Remove a specific breakpoint by reference. */
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
{
#if defined(TARGET_HAS_ICE)
QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
breakpoint_invalidate(cpu, breakpoint->pc);
g_free(breakpoint);
#endif
}
/* Remove all matching breakpoints. */
void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp, *next;
QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
@ -756,14 +743,12 @@ void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
cpu_breakpoint_remove_by_ref(cpu, bp);
}
}
#endif
}
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
void cpu_single_step(CPUState *cpu, int enabled)
{
#if defined(TARGET_HAS_ICE)
if (cpu->singlestep_enabled != enabled) {
cpu->singlestep_enabled = enabled;
if (kvm_enabled()) {
@ -775,7 +760,6 @@ void cpu_single_step(CPUState *cpu, int enabled)
tb_flush(env);
}
}
#endif
}
void cpu_abort(CPUState *cpu, const char *fmt, ...)

4
linux-user/main.c
View File

@ -3436,10 +3436,8 @@ CPUArchState *cpu_copy(CPUArchState *env)
CPUState *cpu = ENV_GET_CPU(env);
CPUArchState *new_env = cpu_init(cpu_model);
CPUState *new_cpu = ENV_GET_CPU(new_env);
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
CPUWatchpoint *wp;
#endif
/* Reset non arch specific state */
cpu_reset(new_cpu);
@ -3451,14 +3449,12 @@ CPUArchState *cpu_copy(CPUArchState *env)
BP_CPU break/watchpoints are handled correctly on clone. */
QTAILQ_INIT(&cpu->breakpoints);
QTAILQ_INIT(&cpu->watchpoints);
#if defined(TARGET_HAS_ICE)
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
}
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
}
#endif
return new_env;
}

2
target-alpha/cpu.h
View File

@ -32,8 +32,6 @@
#include "fpu/softfloat.h"
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_ALPHA
#define ICACHE_LINE_SIZE 32

2
target-arm/cpu.h
View File

@ -39,8 +39,6 @@
#include "fpu/softfloat.h"
#define TARGET_HAS_ICE 1
#define EXCP_UDEF 1 /* undefined instruction */
#define EXCP_SWI 2 /* software interrupt */
#define EXCP_PREFETCH_ABORT 3

2
target-cris/cpu.h
View File

@ -29,8 +29,6 @@
#include "exec/cpu-defs.h"
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_CRIS
#define EXCP_NMI 1

2
target-i386/cpu.h
View File

@ -37,8 +37,6 @@
close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC
#define TARGET_HAS_ICE 1
#ifdef TARGET_X86_64
#define ELF_MACHINE EM_X86_64
#define ELF_MACHINE_UNAME "x86_64"

2
target-lm32/cpu.h
View File

@ -30,8 +30,6 @@
struct CPULM32State;
typedef struct CPULM32State CPULM32State;
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_LATTICEMICO32
#define NB_MMU_MODES 1

2
target-m68k/cpu.h
View File

@ -32,8 +32,6 @@
#define MAX_QREGS 32
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_68K
#define EXCP_ACCESS 2 /* Access (MMU) error. */

2
target-microblaze/cpu.h
View File

@ -34,8 +34,6 @@ typedef struct CPUMBState CPUMBState;
#include "mmu.h"
#endif
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_MICROBLAZE
#define EXCP_NMI 1

1
target-mips/cpu.h
View File

@ -4,7 +4,6 @@
//#define DEBUG_OP
#define ALIGNED_ONLY
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_MIPS

2
target-moxie/cpu.h
View File

@ -26,8 +26,6 @@
#define CPUArchState struct CPUMoxieState
#define TARGET_HAS_ICE 1
#define ELF_MACHINE 0xFEED /* EM_MOXIE */
#define MOXIE_EX_DIV0 0

2
target-ppc/cpu.h
View File

@ -79,8 +79,6 @@
#include "fpu/softfloat.h"
#define TARGET_HAS_ICE 1
#if defined (TARGET_PPC64)
#define ELF_MACHINE EM_PPC64
#else

2
target-s390x/cpu.h
View File

@ -886,8 +886,6 @@ int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
uint64_t vr);
#define TARGET_HAS_ICE 1
/* The value of the TOD clock for 1.1.1970. */
#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL

1
target-sh4/cpu.h
View File

@ -23,7 +23,6 @@
#include "qemu-common.h"
#define TARGET_LONG_BITS 32
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_SH

2
target-sparc/cpu.h
View File

@ -31,8 +31,6 @@
#include "fpu/softfloat.h"
#define TARGET_HAS_ICE 1
#if !defined(TARGET_SPARC64)
#define ELF_MACHINE EM_SPARC
#else

2
target-xtensa/cpu.h
View File

@ -39,8 +39,6 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
#define TARGET_HAS_ICE 1
#define NB_MMU_MODES 4
#define TARGET_PHYS_ADDR_SPACE_BITS 32

4
translate-all.c
View File

@ -1451,7 +1451,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
return &tcg_ctx.tb_ctx.tbs[m_max];
}
#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY)
#if !defined(CONFIG_USER_ONLY)
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
{
ram_addr_t ram_addr;
@ -1467,7 +1467,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+ addr;
tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
}
#endif /* TARGET_HAS_ICE && !defined(CONFIG_USER_ONLY) */
#endif /* !defined(CONFIG_USER_ONLY) */
void tb_check_watchpoint(CPUState *cpu)
{