Don't wrap I2C registers addresses on PXA270.
This way the registers will only be visible at the given offset instead of every 0x100 bytes. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5899 c046a42c-6fe2-441c-8c8c-71466251a162
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11
hw/pxa2xx.c
11
hw/pxa2xx.c
@ -1260,6 +1260,7 @@ struct pxa2xx_i2c_s {
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i2c_slave slave;
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i2c_bus *bus;
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qemu_irq irq;
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target_phys_addr_t offset;
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uint16_t control;
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uint16_t status;
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@ -1340,7 +1341,7 @@ static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
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{
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struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
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addr &= 0xff;
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addr -= s->offset;
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switch (addr) {
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case ICR:
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return s->control;
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@ -1369,7 +1370,7 @@ static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
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struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
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int ack;
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addr &= 0xff;
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addr -= s->offset;
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switch (addr) {
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case ICR:
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s->control = value & 0xfff7;
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@ -1474,7 +1475,7 @@ static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
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}
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struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
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qemu_irq irq, uint32_t page_size)
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qemu_irq irq, uint32_t region_size)
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{
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int iomemtype;
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/* FIXME: Should the slave device really be on a separate bus? */
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@ -1486,10 +1487,12 @@ struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
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s->slave.recv = pxa2xx_i2c_rx;
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s->slave.send = pxa2xx_i2c_tx;
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s->bus = i2c_init_bus();
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s->offset = base & region_size;
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iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
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pxa2xx_i2c_writefn, s);
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cpu_register_physical_memory(base & ~page_size, page_size + 1, iomemtype);
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cpu_register_physical_memory(base & ~region_size,
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region_size + 1, iomemtype);
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register_savevm("pxa2xx_i2c", base, 1,
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pxa2xx_i2c_save, pxa2xx_i2c_load, s);
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