OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

Misc hardware patch queue

Browse Source 
HW emulation:
 - PMBus fixes and tests (Titus)
 - IDE fixes and tests (Fiona)
 - New ADM1266 sensor (Titus)
 - Better error propagation in PCI-ISA i82378 (Philippe)
 - Declare SD model QOM types using DEFINE_TYPES macro (Philippe)
 
 Topology:
 - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu)
 
 Monitor:
 - Synchronize CPU state in 'info lapic' (Dongli Zhang)
 
 QOM:
 - Have 'cpu-qom.h' target-agnostic (Philippe)
 - Move ArchCPUClass definition to each target's cpu.h (Philippe)
 - Call object_class_is_abstract once in cpu_class_by_name (Philippe)
 
 UI:
 - Use correct key names in titles on MacOS / SDL2 (Adrian)
 
 MIPS:
 - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe)
 
 Nios2:
 - Create IRQs *after* vCPU is realized (Philippe)
 
 PPC:
 - Restrict KVM objects to system emulation (Philippe)
 - Move target-specific definitions out of 'cpu-qom.h' (Philippe)
 
 S390X:
 - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe)
 
 X86:
 - HVF & KVM cleanups (Philippe)
 
 Various targets:
 - Use env_archcpu() to optimize (Philippe)
 
 Misc:
 - Few global variable shadowing removed (Philippe)
 - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe)
 - Remove few more 'softmmu' mentions (Philippe)
 - Fix and cleanup in vl.c (Akihiko & Marc-André)
 - Resource leak fix in dump (Zongmin Zhou)
 - MAINTAINERS updates (Thomas, Daniel)
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t
 wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S
 vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q
 jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi
 zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh
 ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan
 DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM
 L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu
 DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z
 HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY
 Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp
 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus=
 =OVdQ
 -----END PGP SIGNATURE-----

Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging

Misc hardware patch queue

HW emulation:
- PMBus fixes and tests (Titus)
- IDE fixes and tests (Fiona)
- New ADM1266 sensor (Titus)
- Better error propagation in PCI-ISA i82378 (Philippe)
- Declare SD model QOM types using DEFINE_TYPES macro (Philippe)

Topology:
- Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu)

Monitor:
- Synchronize CPU state in 'info lapic' (Dongli Zhang)

QOM:
- Have 'cpu-qom.h' target-agnostic (Philippe)
- Move ArchCPUClass definition to each target's cpu.h (Philippe)
- Call object_class_is_abstract once in cpu_class_by_name (Philippe)

UI:
- Use correct key names in titles on MacOS / SDL2 (Adrian)

MIPS:
- Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe)

Nios2:
- Create IRQs *after* vCPU is realized (Philippe)

PPC:
- Restrict KVM objects to system emulation (Philippe)
- Move target-specific definitions out of 'cpu-qom.h' (Philippe)

S390X:
- Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe)

X86:
- HVF & KVM cleanups (Philippe)

Various targets:
- Use env_archcpu() to optimize (Philippe)

Misc:
- Few global variable shadowing removed (Philippe)
- Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe)
- Remove few more 'softmmu' mentions (Philippe)
- Fix and cleanup in vl.c (Akihiko & Marc-André)
- Resource leak fix in dump (Zongmin Zhou)
- MAINTAINERS updates (Thomas, Daniel)

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t
# wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S
# vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q
# jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi
# zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh
# ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan
# DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM
# L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu
# DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z
# HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY
# Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp
# 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus=
# =OVdQ
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits)
  dump: Add close fd on error return to avoid resource leak
  ui/sdl2: use correct key names in win title on mac
  MAINTAINERS: Add more guest-agent related files to the corresponding section
  MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section
  MAINTAINERS: update libvirt devel mailing list address
  MAINTAINERS: Add the CAN documentation file to the CAN section
  MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section
  hw/sd: Declare QOM types using DEFINE_TYPES() macro
  hw/i2c: pmbus: reset page register for out of range reads
  hw/i2c: pmbus: immediately clear faults on request
  tests/qtest: add tests for ADM1266
  hw/sensor: add ADM1266 device model
  hw/i2c: pmbus: add VCAP register
  hw/i2c: pmbus: add fan support
  hw/i2c: pmbus: add vout mode bitfields
  hw/i2c: pmbus add support for block receive
  tests/qtest: ahci-test: add test exposing reset issue with pending callback
  hw/ide: reset: cancel async DMA operation before resetting state
  hw/cpu: Update the comments of nr_cores and nr_dies
  system/cpus: Fix CPUState.nr_cores' calculation
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-08 08:32:26 +08:00
commit ed1d873caa
134 changed files with 1722 additions and 1085 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
MAINTAINERS
View File

@ -859,8 +859,10 @@ M: Hao Wu <wuhaotsh@google.com>
L: qemu-arm@nongnu.org
S: Supported
F: hw/*/npcm*
F: hw/sensor/adm1266.c
F: include/hw/*/npcm*
F: tests/qtest/npcm*
F: tests/qtest/adm1266-test.c
F: pc-bios/npcm7xx_bootrom.bin
F: roms/vbootrom
F: docs/system/arm/nuvoton.rst
@ -1615,6 +1617,7 @@ F: hw/intc/sh_intc.c
F: hw/pci-host/sh_pci.c
F: hw/timer/sh_timer.c
F: include/hw/sh4/sh_intc.h
F: include/hw/timer/tmu012.h
Shix
R: Yoshinori Sato <ysato@users.sourceforge.jp>
@ -1772,7 +1775,7 @@ F: include/hw/southbridge/ich9.h
F: include/hw/southbridge/piix.h
F: hw/isa/apm.c
F: include/hw/isa/apm.h
F: tests/unit/test-x86-cpuid.c
F: tests/unit/test-x86-topo.c
F: tests/qtest/test-x86-cpuid-compat.c
PC Chipset
@ -1858,6 +1861,7 @@ M: Max Filippov <jcmvbkbc@gmail.com>
S: Maintained
F: hw/xtensa/xtfpga.c
F: hw/net/opencores_eth.c
F: include/hw/xtensa/mx_pic.h
Devices
-------
@ -2594,6 +2598,7 @@ W: https://canbus.pages.fel.cvut.cz/
F: net/can/*
F: hw/net/can/*
F: include/net/can_*.h
F: docs/system/devices/can.rst
OpenPIC interrupt controller
M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
@ -3149,10 +3154,11 @@ M: Michael Roth <michael.roth@amd.com>
M: Konstantin Kostiuk <kkostiuk@redhat.com>
S: Maintained
F: qga/
F: contrib/systemd/qemu-guest-agent.service
F: docs/interop/qemu-ga.rst
F: docs/interop/qemu-ga-ref.rst
F: scripts/qemu-guest-agent/
F: tests/unit/test-qga.c
F: tests/*/test-qga*
T: git https://github.com/mdroth/qemu.git qga
QEMU Guest Agent Win32
@ -4062,7 +4068,7 @@ F: gitdm.config
F: contrib/gitdm/*
Incompatible changes
R: libvir-list@redhat.com
R: devel@lists.libvirt.org
F: docs/about/deprecated.rst
Build System

4
accel/stubs/tcg-stub.c
View File

@ -22,10 +22,6 @@ void tlb_set_dirty(CPUState *cpu, vaddr vaddr)
{
}
void tcg_flush_jmp_cache(CPUState *cpu)
{
}
int probe_access_flags(CPUArchState *env, vaddr addr, int size,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost, uintptr_t retaddr)

1
accel/tcg/cputlb.c
View File

@ -24,6 +24,7 @@
#include "exec/memory.h"
#include "exec/cpu_ldst.h"
#include "exec/cputlb.h"
#include "exec/tb-flush.h"
#include "exec/memory-internal.h"
#include "exec/ram_addr.h"
#include "tcg/tcg.h"

9
accel/tcg/tcg-accel-ops.c
View File

@ -34,6 +34,7 @@
#include "qemu/timer.h"
#include "exec/exec-all.h"
#include "exec/hwaddr.h"
#include "exec/tb-flush.h"
#include "exec/gdbstub.h"
#include "tcg-accel-ops.h"
@ -77,6 +78,13 @@ int tcg_cpus_exec(CPUState *cpu)
return ret;
}
static void tcg_cpu_reset_hold(CPUState *cpu)
{
tcg_flush_jmp_cache(cpu);
tlb_flush(cpu);
}
/* mask must never be zero, except for A20 change call */
void tcg_handle_interrupt(CPUState *cpu, int mask)
{
@ -205,6 +213,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops)
}
}
ops->cpu_reset_hold = tcg_cpu_reset_hold;
ops->supports_guest_debug = tcg_supports_guest_debug;
ops->insert_breakpoint = tcg_insert_breakpoint;
ops->remove_breakpoint = tcg_remove_breakpoint;

8
accel/tcg/translate-all.c
View File

@ -673,11 +673,3 @@ void tcg_flush_jmp_cache(CPUState *cpu)
qatomic_set(&jc->array[i].tb, NULL);
}
}
/* This is a wrapper for common code that can not use CONFIG_SOFTMMU */
void tcg_flush_softmmu_tlb(CPUState *cs)
{
#ifdef CONFIG_SOFTMMU
tlb_flush(cs);
#endif
}

4
accel/tcg/user-exec-stub.c
View File

@ -14,6 +14,10 @@ void qemu_init_vcpu(CPUState *cpu)
{
}
void cpu_exec_reset_hold(CPUState *cpu)
{
}
/* User mode emulation does not support record/replay yet. */
bool replay_exception(void)

2
bsd-user/main.c
View File

@ -118,7 +118,7 @@ void fork_end(int child)
*/
CPU_FOREACH_SAFE(cpu, next_cpu) {
if (cpu != thread_cpu) {
QTAILQ_REMOVE_RCU(&cpus, cpu, node);
QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node);
}
}
mmap_fork_end(child);

6
cpu-common.c
View File

@ -73,7 +73,7 @@ static int cpu_get_free_index(void)
return max_cpu_index;
}
CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
CPUTailQ cpus_queue = QTAILQ_HEAD_INITIALIZER(cpus_queue);
static unsigned int cpu_list_generation_id;
unsigned int cpu_list_generation_id_get(void)
@ -90,7 +90,7 @@ void cpu_list_add(CPUState *cpu)
} else {
assert(!cpu_index_auto_assigned);
}
QTAILQ_INSERT_TAIL_RCU(&cpus, cpu, node);
QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node);
cpu_list_generation_id++;
}
@ -102,7 +102,7 @@ void cpu_list_remove(CPUState *cpu)
return;
}
QTAILQ_REMOVE_RCU(&cpus, cpu, node);
QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu_list_generation_id++;
}

6
cpu-target.c
View File

@ -131,13 +131,13 @@ const VMStateDescription vmstate_cpu_common = {
};
#endif
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
/* cache the cpu class for the hotpath */
cpu->cc = CPU_GET_CLASS(cpu);
if (!accel_cpu_common_realize(cpu, errp)) {
return;
return false;
}
/* Wait until cpu initialization complete before exposing cpu. */
@ -159,6 +159,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
return true;
}
void cpu_exec_unrealizefn(CPUState *cpu)

1
dump/dump.c
View File

@ -2160,6 +2160,7 @@ void qmp_dump_guest_memory(bool paging, const char *protocol,
return;
}
if (kdump_raw && lseek(fd, 0, SEEK_CUR) == (off_t) -1) {
close(fd);
error_setg(errp, "kdump-raw formats require a seekable file");
return;
}

1
hw/arm/Kconfig
View File

@ -491,6 +491,7 @@ config NPCM7XX
default y
depends on TCG && ARM
select A9MPCORE
select ADM1266
select ADM1272
select ARM_GIC
select SMBUS

19
hw/core/cpu-common.c
View File

@ -136,10 +136,7 @@ static void cpu_common_reset_hold(Object *obj)
cpu->crash_occurred = false;
cpu->cflags_next_tb = -1;
if (tcg_enabled()) {
tcg_flush_jmp_cache(cpu);
tcg_flush_softmmu_tlb(cpu);
}
cpu_exec_reset_hold(cpu);
}
static bool cpu_common_has_work(CPUState *cs)
@ -149,10 +146,18 @@ static bool cpu_common_has_work(CPUState *cs)
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
{
CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
ObjectClass *oc;
CPUClass *cc;
assert(cpu_model && cc->class_by_name);
return cc->class_by_name(cpu_model);
oc = object_class_by_name(typename);
cc = CPU_CLASS(oc);
assert(cc->class_by_name);
assert(cpu_model);
oc = cc->class_by_name(cpu_model);
if (oc == NULL || object_class_is_abstract(oc)) {
return NULL;
}
return oc;
}
static void cpu_common_parse_features(const char *typename, char *features,

4
hw/core/loader.c
View File

@ -1070,7 +1070,7 @@ static void *rom_set_mr(Rom *rom, Object *owner, const char *name, bool ro)
ssize_t rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex,
bool option_rom, MemoryRegion *mr,
bool has_option_rom, MemoryRegion *mr,
AddressSpace *as)
{
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
@ -1139,7 +1139,7 @@ ssize_t rom_add_file(const char *file, const char *fw_dir,
basename);
snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name);
if ((!option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) {
if ((!has_option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) {
data = rom_set_mr(rom, OBJECT(fw_cfg), devpath, true);
} else {
data = rom->data;

237
hw/i2c/pmbus_device.c
View File

@ -102,7 +102,6 @@ void pmbus_send_string(PMBusDevice *pmdev, const char *data)
}
size_t len = strlen(data);
g_assert(len > 0);
g_assert(len + pmdev->out_buf_len < SMBUS_DATA_MAX_LEN);
pmdev->out_buf[len + pmdev->out_buf_len] = len;
@ -112,6 +111,35 @@ void pmbus_send_string(PMBusDevice *pmdev, const char *data)
pmdev->out_buf_len += len + 1;
}
uint8_t pmbus_receive_block(PMBusDevice *pmdev, uint8_t *dest, size_t len)
{
/* dest may contain data from previous writes */
memset(dest, 0, len);
/* Exclude command code from return value */
pmdev->in_buf++;
pmdev->in_buf_len--;
/* The byte after the command code denotes the length */
uint8_t sent_len = pmdev->in_buf[0];
if (sent_len != pmdev->in_buf_len - 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: length mismatch. Expected %d bytes, got %d bytes\n",
__func__, sent_len, pmdev->in_buf_len - 1);
}
/* exclude length byte */
pmdev->in_buf++;
pmdev->in_buf_len--;
if (pmdev->in_buf_len < len) {
len = pmdev->in_buf_len;
}
memcpy(dest, pmdev->in_buf, len);
return len;
}
static uint64_t pmbus_receive_uint(PMBusDevice *pmdev)
{
@ -472,6 +500,54 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
}
break;
case PMBUS_FAN_CONFIG_1_2: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].fan_config_1_2);
} else {
goto passthough;
}
break;
case PMBUS_FAN_COMMAND_1: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].fan_command_1);
} else {
goto passthough;
}
break;
case PMBUS_FAN_COMMAND_2: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].fan_command_2);
} else {
goto passthough;
}
break;
case PMBUS_FAN_CONFIG_3_4: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].fan_config_3_4);
} else {
goto passthough;
}
break;
case PMBUS_FAN_COMMAND_3: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].fan_command_3);
} else {
goto passthough;
}
break;
case PMBUS_FAN_COMMAND_4: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].fan_command_4);
} else {
goto passthough;
}
break;
case PMBUS_VOUT_OV_FAULT_LIMIT: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_VOUT) {
pmbus_send16(pmdev, pmdev->pages[index].vout_ov_fault_limit);
@ -782,6 +858,22 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
pmbus_send8(pmdev, pmdev->pages[index].status_mfr_specific);
break;
case PMBUS_STATUS_FANS_1_2: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].status_fans_1_2);
} else {
goto passthough;
}
break;
case PMBUS_STATUS_FANS_3_4: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].status_fans_3_4);
} else {
goto passthough;
}
break;
case PMBUS_READ_EIN: /* Read-Only block 5 bytes */
if (pmdev->pages[index].page_flags & PB_HAS_EIN) {
pmbus_send(pmdev, pmdev->pages[index].read_ein, 5);
@ -814,6 +906,14 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
}
break;
case PMBUS_READ_VCAP: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_VCAP) {
pmbus_send16(pmdev, pmdev->pages[index].read_vcap);
} else {
goto passthough;
}
break;
case PMBUS_READ_VOUT: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_VOUT) {
pmbus_send16(pmdev, pmdev->pages[index].read_vout);
@ -854,6 +954,54 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd)
}
break;
case PMBUS_READ_FAN_SPEED_1: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_1);
} else {
goto passthough;
}
break;
case PMBUS_READ_FAN_SPEED_2: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_2);
} else {
goto passthough;
}
break;
case PMBUS_READ_FAN_SPEED_3: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_3);
} else {
goto passthough;
}
break;
case PMBUS_READ_FAN_SPEED_4: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_4);
} else {
goto passthough;
}
break;
case PMBUS_READ_DUTY_CYCLE: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_duty_cycle);
} else {
goto passthough;
}
break;
case PMBUS_READ_FREQUENCY: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send16(pmdev, pmdev->pages[index].read_frequency);
} else {
goto passthough;
}
break;
case PMBUS_READ_POUT: /* Read-Only word */
if (pmdev->pages[index].page_flags & PB_HAS_POUT) {
pmbus_send16(pmdev, pmdev->pages[index].read_pout);
@ -1096,12 +1244,26 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
pmdev->in_buf = buf;
pmdev->code = buf[0]; /* PMBus command code */
if (pmdev->code == PMBUS_CLEAR_FAULTS) {
pmbus_clear_faults(pmdev);
}
if (len == 1) { /* Single length writes are command codes only */
return 0;
}
if (pmdev->code == PMBUS_PAGE) {
pmdev->page = pmbus_receive8(pmdev);
if (pmdev->page > pmdev->num_pages - 1 && pmdev->page != PB_ALL_PAGES) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: page %u is out of range\n",
__func__, pmdev->page);
pmdev->page = 0; /* undefined behaviour - reset to page 0 */
pmbus_cml_error(pmdev);
return PMBUS_ERR_BYTE;
}
return 0;
}
@ -1115,15 +1277,6 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
return 0;
}
if (pmdev->page > pmdev->num_pages - 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: page %u is out of range\n",
__func__, pmdev->page);
pmdev->page = 0; /* undefined behaviour - reset to page 0 */
pmbus_cml_error(pmdev);
return PMBUS_ERR_BYTE;
}
index = pmdev->page;
switch (pmdev->code) {
@ -1277,6 +1430,54 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
}
break;
case PMBUS_FAN_CONFIG_1_2: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_config_1_2 = pmbus_receive8(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_COMMAND_1: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_command_1 = pmbus_receive16(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_COMMAND_2: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_command_2 = pmbus_receive16(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_CONFIG_3_4: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_config_3_4 = pmbus_receive8(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_COMMAND_3: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_command_3 = pmbus_receive16(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_FAN_COMMAND_4: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmdev->pages[index].fan_command_4 = pmbus_receive16(pmdev);
} else {
goto passthrough;
}
break;
case PMBUS_VOUT_OV_FAULT_LIMIT: /* R/W word */
if (pmdev->pages[index].page_flags & PB_HAS_VOUT) {
pmdev->pages[index].vout_ov_fault_limit = pmbus_receive16(pmdev);
@ -1582,6 +1783,22 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len)
pmdev->pages[index].status_mfr_specific = pmbus_receive8(pmdev);
break;
case PMBUS_STATUS_FANS_1_2: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].status_fans_1_2);
} else {
goto passthrough;
}
break;
case PMBUS_STATUS_FANS_3_4: /* R/W byte */
if (pmdev->pages[index].page_flags & PB_HAS_FAN) {
pmbus_send8(pmdev, pmdev->pages[index].status_fans_3_4);
} else {
goto passthrough;
}
break;
case PMBUS_PAGE_PLUS_READ: /* Block Read-only */
case PMBUS_CAPABILITY: /* Read-Only byte */
case PMBUS_COEFFICIENTS: /* Read-only block 5 bytes */

14
hw/ide/core.c
View File

@ -2515,19 +2515,19 @@ static void ide_dummy_transfer_stop(IDEState *s)
void ide_bus_reset(IDEBus *bus)
{
bus->unit = 0;
bus->cmd = 0;
ide_reset(&bus->ifs[0]);
ide_reset(&bus->ifs[1]);
ide_clear_hob(bus);
/* pending async DMA */
/* pending async DMA - needs the IDEState before it is reset */
if (bus->dma->aiocb) {
trace_ide_bus_reset_aio();
blk_aio_cancel(bus->dma->aiocb);
bus->dma->aiocb = NULL;
}
bus->unit = 0;
bus->cmd = 0;
ide_reset(&bus->ifs[0]);
ide_reset(&bus->ifs[1]);
ide_clear_hob(bus);
/* reset dma provider too */
if (bus->dma->ops->reset) {
bus->dma->ops->reset(bus->dma);

4
hw/isa/i82378.c
View File

@ -105,7 +105,9 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
/* speaker */
pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal);
isa_realize_and_unref(pcspk, isabus, &error_fatal);
if (!isa_realize_and_unref(pcspk, isabus, errp)) {
return;
}
/* 2 82C37 (dma) */
isa_create_simple(isabus, "i82374");

4
hw/ppc/e500.c
View File

@ -834,6 +834,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
IrqLines *irqs, Error **errp)
{
#ifdef CONFIG_KVM
DeviceState *dev;
CPUState *cs;
@ -854,6 +855,9 @@ static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
}
return dev;
#else
g_assert_not_reached();
#endif
}
static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,

3
hw/s390x/css.c
View File

@ -644,8 +644,9 @@ void css_conditional_io_interrupt(SubchDev *sch)
}
}
int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode)
{
CPUS390XState *env = &cpu->env;
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = s390_get_flic_class(fs);
int r;

7
hw/s390x/sclp.c
View File

@ -269,9 +269,9 @@ static void sclp_execute(SCLPDevice *sclp, SCCB *sccb, uint32_t code)
* service_interrupt call.
*/
#define SCLP_PV_DUMMY_ADDR 0x4000
int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb,
uint32_t code)
int sclp_service_call_protected(S390CPU *cpu, uint64_t sccb, uint32_t code)
{
CPUS390XState *env = &cpu->env;
SCLPDevice *sclp = get_sclp_device();
SCLPDeviceClass *sclp_c = SCLP_GET_CLASS(sclp);
SCCBHeader header;
@ -296,8 +296,9 @@ out_write:
return 0;
}
int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code)
int sclp_service_call(S390CPU *cpu, uint64_t sccb, uint32_t code)
{
CPUS390XState *env = &cpu->env;
SCLPDevice *sclp = get_sclp_device();
SCLPDeviceClass *sclp_c = SCLP_GET_CLASS(sclp);
SCCBHeader header;

19
hw/sd/aspeed_sdhci.c
View File

@ -198,16 +198,13 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
device_class_set_props(dc, aspeed_sdhci_properties);
}
static const TypeInfo aspeed_sdhci_info = {
.name = TYPE_ASPEED_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedSDHCIState),
.class_init = aspeed_sdhci_class_init,
static const TypeInfo aspeed_sdhci_types[] = {
{
.name = TYPE_ASPEED_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedSDHCIState),
.class_init = aspeed_sdhci_class_init,
},
};
static void aspeed_sdhci_register_types(void)
{
type_register_static(&aspeed_sdhci_info);
}
type_init(aspeed_sdhci_register_types)
DEFINE_TYPES(aspeed_sdhci_types)

33
hw/sd/bcm2835_sdhost.c
View File

@ -436,24 +436,19 @@ static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_sdhost;
}
static const TypeInfo bcm2835_sdhost_info = {
.name = TYPE_BCM2835_SDHOST,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835SDHostState),
.class_init = bcm2835_sdhost_class_init,
.instance_init = bcm2835_sdhost_init,
static const TypeInfo bcm2835_sdhost_types[] = {
{
.name = TYPE_BCM2835_SDHOST,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BCM2835SDHostState),
.class_init = bcm2835_sdhost_class_init,
.instance_init = bcm2835_sdhost_init,
},
{
.name = TYPE_BCM2835_SDHOST_BUS,
.parent = TYPE_SD_BUS,
.instance_size = sizeof(SDBus),
},
};
static const TypeInfo bcm2835_sdhost_bus_info = {
.name = TYPE_BCM2835_SDHOST_BUS,
.parent = TYPE_SD_BUS,
.instance_size = sizeof(SDBus),
};
static void bcm2835_sdhost_register_types(void)
{
type_register_static(&bcm2835_sdhost_info);
type_register_static(&bcm2835_sdhost_bus_info);
}
type_init(bcm2835_sdhost_register_types)
DEFINE_TYPES(bcm2835_sdhost_types)

21
hw/sd/cadence_sdhci.c
View File

@ -175,17 +175,14 @@ static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
dc->vmsd = &vmstate_cadence_sdhci;
}
static const TypeInfo cadence_sdhci_info = {
.name = TYPE_CADENCE_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(CadenceSDHCIState),
.instance_init = cadence_sdhci_instance_init,
.class_init = cadence_sdhci_class_init,
static const TypeInfo cadence_sdhci_types[] = {
{
.name = TYPE_CADENCE_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(CadenceSDHCIState),
.instance_init = cadence_sdhci_instance_init,
.class_init = cadence_sdhci_class_init,
},
};
static void cadence_sdhci_register_types(void)
{
type_register_static(&cadence_sdhci_info);
}
type_init(cadence_sdhci_register_types)
DEFINE_TYPES(cadence_sdhci_types)

19
hw/sd/core.c
View File

@ -259,16 +259,13 @@ void sdbus_reparent_card(SDBus *from, SDBus *to)
sdbus_set_readonly(to, readonly);
}
static const TypeInfo sd_bus_info = {
.name = TYPE_SD_BUS,
.parent = TYPE_BUS,
.instance_size = sizeof(SDBus),
.class_size = sizeof(SDBusClass),
static const TypeInfo sd_bus_types[] = {
{
.name = TYPE_SD_BUS,
.parent = TYPE_BUS,
.instance_size = sizeof(SDBus),
.class_size = sizeof(SDBusClass),
},
};
static void sd_bus_register_types(void)
{
type_register_static(&sd_bus_info);
}
type_init(sd_bus_register_types)
DEFINE_TYPES(sd_bus_types)

21
hw/sd/npcm7xx_sdhci.c
View File

@ -166,17 +166,14 @@ static void npcm7xx_sdhci_instance_init(Object *obj)
TYPE_SYSBUS_SDHCI);
}
static const TypeInfo npcm7xx_sdhci_info = {
.name = TYPE_NPCM7XX_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxSDHCIState),
.instance_init = npcm7xx_sdhci_instance_init,
.class_init = npcm7xx_sdhci_class_init,
static const TypeInfo npcm7xx_sdhci_types[] = {
{
.name = TYPE_NPCM7XX_SDHCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxSDHCIState),
.instance_init = npcm7xx_sdhci_instance_init,
.class_init = npcm7xx_sdhci_class_init,
},
};
static void npcm7xx_sdhci_register_types(void)
{
type_register_static(&npcm7xx_sdhci_info);
}
type_init(npcm7xx_sdhci_register_types)
DEFINE_TYPES(npcm7xx_sdhci_types)

35
hw/sd/pl181.c
View File

@ -519,14 +519,6 @@ static void pl181_class_init(ObjectClass *klass, void *data)
k->user_creatable = false;
}
static const TypeInfo pl181_info = {
.name = TYPE_PL181,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PL181State),
.instance_init = pl181_init,
.class_init = pl181_class_init,
};
static void pl181_bus_class_init(ObjectClass *klass, void *data)
{
SDBusClass *sbc = SD_BUS_CLASS(klass);
@ -535,17 +527,20 @@ static void pl181_bus_class_init(ObjectClass *klass, void *data)
sbc->set_readonly = pl181_set_readonly;
}
static const TypeInfo pl181_bus_info = {
.name = TYPE_PL181_BUS,
.parent = TYPE_SD_BUS,
.instance_size = sizeof(SDBus),
.class_init = pl181_bus_class_init,
static const TypeInfo pl181_info[] = {
{
.name = TYPE_PL181,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PL181State),
.instance_init = pl181_init,
.class_init = pl181_class_init,
},
{
.name = TYPE_PL181_BUS,
.parent = TYPE_SD_BUS,
.instance_size = sizeof(SDBus),
.class_init = pl181_bus_class_init,
},
};
static void pl181_register_types(void)
{
type_register_static(&pl181_info);
type_register_static(&pl181_bus_info);
}
type_init(pl181_register_types)
DEFINE_TYPES(pl181_info)

35
hw/sd/pxa2xx_mmci.c
View File

@ -575,25 +575,20 @@ static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
sbc->set_readonly = pxa2xx_mmci_set_readonly;
}
static const TypeInfo pxa2xx_mmci_info = {
.name = TYPE_PXA2XX_MMCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxMMCIState),
.instance_init = pxa2xx_mmci_instance_init,
.class_init = pxa2xx_mmci_class_init,
static const TypeInfo pxa2xx_mmci_types[] = {
{
.name = TYPE_PXA2XX_MMCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxMMCIState),
.instance_init = pxa2xx_mmci_instance_init,
.class_init = pxa2xx_mmci_class_init,
},
{
.name = TYPE_PXA2XX_MMCI_BUS,
.parent = TYPE_SD_BUS,
.instance_size = sizeof(SDBus),
.class_init = pxa2xx_mmci_bus_class_init,
},
};
static const TypeInfo pxa2xx_mmci_bus_info = {
.name = TYPE_PXA2XX_MMCI_BUS,
.parent = TYPE_SD_BUS,
.instance_size = sizeof(SDBus),
.class_init = pxa2xx_mmci_bus_class_init,
};
static void pxa2xx_mmci_register_types(void)
{
type_register_static(&pxa2xx_mmci_info);
type_register_static(&pxa2xx_mmci_bus_info);
}
type_init(pxa2xx_mmci_register_types)
DEFINE_TYPES(pxa2xx_mmci_types)

37
hw/sd/sd.c
View File

@ -2278,16 +2278,6 @@ static void sd_class_init(ObjectClass *klass, void *data)
sc->proto = &sd_proto_sd;
}
static const TypeInfo sd_info = {
.name = TYPE_SD_CARD,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SDState),
.class_size = sizeof(SDCardClass),
.class_init = sd_class_init,
.instance_init = sd_instance_init,
.instance_finalize = sd_instance_finalize,
};
/*
* We do not model the chip select pin, so allow the board to select
* whether card should be in SSI or MMC/SD mode. It is also up to the
@ -2303,16 +2293,21 @@ static void sd_spi_class_init(ObjectClass *klass, void *data)
sc->proto = &sd_proto_spi;
}
static const TypeInfo sd_spi_info = {
.name = TYPE_SD_CARD_SPI,
.parent = TYPE_SD_CARD,
.class_init = sd_spi_class_init,
static const TypeInfo sd_types[] = {
{
.name = TYPE_SD_CARD,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SDState),
.class_size = sizeof(SDCardClass),
.class_init = sd_class_init,
.instance_init = sd_instance_init,
.instance_finalize = sd_instance_finalize,
},
{
.name = TYPE_SD_CARD_SPI,
.parent = TYPE_SD_CARD,
.class_init = sd_spi_class_init,
},
};
static void sd_register_types(void)
{
type_register_static(&sd_info);
type_register_static(&sd_spi_info);
}
type_init(sd_register_types)
DEFINE_TYPES(sd_types)

25
hw/sd/sdhci-pci.c
View File

@ -68,20 +68,17 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
sdhci_common_class_init(klass, data);
}
static const TypeInfo sdhci_pci_info = {
.name = TYPE_PCI_SDHCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(SDHCIState),
.class_init = sdhci_pci_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
static const TypeInfo sdhci_pci_types[] = {
{
.name = TYPE_PCI_SDHCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(SDHCIState),
.class_init = sdhci_pci_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
},
};
static void sdhci_pci_register_type(void)
{
type_register_static(&sdhci_pci_info);
}
type_init(sdhci_pci_register_type)
DEFINE_TYPES(sdhci_pci_types)

19
hw/sd/ssi-sd.c
View File

@ -403,16 +403,13 @@ static void ssi_sd_class_init(ObjectClass *klass, void *data)
dc->user_creatable = false;
}
static const TypeInfo ssi_sd_info = {
.name = TYPE_SSI_SD,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(ssi_sd_state),
.class_init = ssi_sd_class_init,
static const TypeInfo ssi_sd_types[] = {
{
.name = TYPE_SSI_SD,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(ssi_sd_state),
.class_init = ssi_sd_class_init,
},
};
static void ssi_sd_register_types(void)
{
type_register_static(&ssi_sd_info);
}
type_init(ssi_sd_register_types)
DEFINE_TYPES(ssi_sd_types)

5
hw/sensor/Kconfig
View File

@ -22,6 +22,11 @@ config ADM1272
bool
depends on I2C
config ADM1266
bool
depends on PMBUS
default y if PMBUS
config MAX34451
bool
depends on I2C

254
hw/sensor/adm1266.c Normal file
View File

@ -0,0 +1,254 @@
/*
* Analog Devices ADM1266 Cascadable Super Sequencer with Margin Control and
* Fault Recording with PMBus
*
* https://www.analog.com/media/en/technical-documentation/data-sheets/adm1266.pdf
*
* Copyright 2023 Google LLC
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "hw/i2c/pmbus_device.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "qemu/log.h"
#include "qemu/module.h"
#define TYPE_ADM1266 "adm1266"
OBJECT_DECLARE_SIMPLE_TYPE(ADM1266State, ADM1266)
#define ADM1266_BLACKBOX_CONFIG 0xD3
#define ADM1266_PDIO_CONFIG 0xD4
#define ADM1266_READ_STATE 0xD9
#define ADM1266_READ_BLACKBOX 0xDE
#define ADM1266_SET_RTC 0xDF
#define ADM1266_GPIO_SYNC_CONFIGURATION 0xE1
#define ADM1266_BLACKBOX_INFORMATION 0xE6
#define ADM1266_PDIO_STATUS 0xE9
#define ADM1266_GPIO_STATUS 0xEA
/* Defaults */
#define ADM1266_OPERATION_DEFAULT 0x80
#define ADM1266_CAPABILITY_DEFAULT 0xA0
#define ADM1266_CAPABILITY_NO_PEC 0x20
#define ADM1266_PMBUS_REVISION_DEFAULT 0x22
#define ADM1266_MFR_ID_DEFAULT "ADI"
#define ADM1266_MFR_ID_DEFAULT_LEN 32
#define ADM1266_MFR_MODEL_DEFAULT "ADM1266-A1"
#define ADM1266_MFR_MODEL_DEFAULT_LEN 32
#define ADM1266_MFR_REVISION_DEFAULT "25"
#define ADM1266_MFR_REVISION_DEFAULT_LEN 8
#define ADM1266_NUM_PAGES 17
/**
* PAGE Index
* Page 0 VH1.
* Page 1 VH2.
* Page 2 VH3.
* Page 3 VH4.
* Page 4 VP1.
* Page 5 VP2.
* Page 6 VP3.
* Page 7 VP4.
* Page 8 VP5.
* Page 9 VP6.
* Page 10 VP7.
* Page 11 VP8.
* Page 12 VP9.
* Page 13 VP10.
* Page 14 VP11.
* Page 15 VP12.
* Page 16 VP13.
*/
typedef struct ADM1266State {
PMBusDevice parent;
char mfr_id[32];
char mfr_model[32];
char mfr_rev[8];
} ADM1266State;
static const uint8_t adm1266_ic_device_id[] = {0x03, 0x41, 0x12, 0x66};
static const uint8_t adm1266_ic_device_rev[] = {0x08, 0x01, 0x08, 0x07, 0x0,
0x0, 0x07, 0x41, 0x30};
static void adm1266_exit_reset(Object *obj)
{
ADM1266State *s = ADM1266(obj);
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
pmdev->page = 0;
pmdev->capability = ADM1266_CAPABILITY_NO_PEC;
for (int i = 0; i < ADM1266_NUM_PAGES; i++) {
pmdev->pages[i].operation = ADM1266_OPERATION_DEFAULT;
pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT;
pmdev->pages[i].vout_mode = 0;
pmdev->pages[i].read_vout = pmbus_data2linear_mode(12, 0);
pmdev->pages[i].vout_margin_high = pmbus_data2linear_mode(15, 0);
pmdev->pages[i].vout_margin_low = pmbus_data2linear_mode(3, 0);
pmdev->pages[i].vout_ov_fault_limit = pmbus_data2linear_mode(16, 0);
pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT;
}
strncpy(s->mfr_id, ADM1266_MFR_ID_DEFAULT, 4);
strncpy(s->mfr_model, ADM1266_MFR_MODEL_DEFAULT, 11);
strncpy(s->mfr_rev, ADM1266_MFR_REVISION_DEFAULT, 3);
}
static uint8_t adm1266_read_byte(PMBusDevice *pmdev)
{
ADM1266State *s = ADM1266(pmdev);
switch (pmdev->code) {
case PMBUS_MFR_ID: /* R/W block */
pmbus_send_string(pmdev, s->mfr_id);
break;
case PMBUS_MFR_MODEL: /* R/W block */
pmbus_send_string(pmdev, s->mfr_model);
break;
case PMBUS_MFR_REVISION: /* R/W block */
pmbus_send_string(pmdev, s->mfr_rev);
break;
case PMBUS_IC_DEVICE_ID:
pmbus_send(pmdev, adm1266_ic_device_id, sizeof(adm1266_ic_device_id));
break;
case PMBUS_IC_DEVICE_REV:
pmbus_send(pmdev, adm1266_ic_device_rev, sizeof(adm1266_ic_device_rev));
break;
default:
qemu_log_mask(LOG_UNIMP,
"%s: reading from unimplemented register: 0x%02x\n",
__func__, pmdev->code);
return 0xFF;
}
return 0;
}
static int adm1266_write_data(PMBusDevice *pmdev, const uint8_t *buf,
uint8_t len)
{
ADM1266State *s = ADM1266(pmdev);
switch (pmdev->code) {
case PMBUS_MFR_ID: /* R/W block */
pmbus_receive_block(pmdev, (uint8_t *)s->mfr_id, sizeof(s->mfr_id));
break;
case PMBUS_MFR_MODEL: /* R/W block */
pmbus_receive_block(pmdev, (uint8_t *)s->mfr_model,
sizeof(s->mfr_model));
break;
case PMBUS_MFR_REVISION: /* R/W block*/
pmbus_receive_block(pmdev, (uint8_t *)s->mfr_rev, sizeof(s->mfr_rev));
break;
case ADM1266_SET_RTC: /* do nothing */
break;
default:
qemu_log_mask(LOG_UNIMP,
"%s: writing to unimplemented register: 0x%02x\n",
__func__, pmdev->code);
break;
}
return 0;
}
static void adm1266_get(Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp)
{
uint16_t value;
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
PMBusVoutMode *mode = (PMBusVoutMode *)&pmdev->pages[0].vout_mode;
if (strcmp(name, "vout") == 0) {
value = pmbus_linear_mode2data(*(uint16_t *)opaque, mode->exp);
} else {
value = *(uint16_t *)opaque;
}
visit_type_uint16(v, name, &value, errp);
}
static void adm1266_set(Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp)
{
uint16_t *internal = opaque;
uint16_t value;
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
PMBusVoutMode *mode = (PMBusVoutMode *)&pmdev->pages[0].vout_mode;
if (!visit_type_uint16(v, name, &value, errp)) {
return;
}
*internal = pmbus_data2linear_mode(value, mode->exp);
pmbus_check_limits(pmdev);
}
static const VMStateDescription vmstate_adm1266 = {
.name = "ADM1266",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]){
VMSTATE_PMBUS_DEVICE(parent, ADM1266State),
VMSTATE_END_OF_LIST()
}
};
static void adm1266_init(Object *obj)
{
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
uint64_t flags = PB_HAS_VOUT_MODE | PB_HAS_VOUT | PB_HAS_VOUT_MARGIN |
PB_HAS_VOUT_RATING | PB_HAS_STATUS_MFR_SPECIFIC;
for (int i = 0; i < ADM1266_NUM_PAGES; i++) {
pmbus_page_config(pmdev, i, flags);
object_property_add(obj, "vout[*]", "uint16",
adm1266_get,
adm1266_set, NULL, &pmdev->pages[i].read_vout);
}
}
static void adm1266_class_init(ObjectClass *klass, void *data)
{
ResettableClass *rc = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
PMBusDeviceClass *k = PMBUS_DEVICE_CLASS(klass);
dc->desc = "Analog Devices ADM1266 Hot Swap controller";
dc->vmsd = &vmstate_adm1266;
k->write_data = adm1266_write_data;
k->receive_byte = adm1266_read_byte;
k->device_num_pages = 17;
rc->phases.exit = adm1266_exit_reset;
}
static const TypeInfo adm1266_info = {
.name = TYPE_ADM1266,
.parent = TYPE_PMBUS_DEVICE,
.instance_size = sizeof(ADM1266State),
.instance_init = adm1266_init,
.class_init = adm1266_class_init,
};
static void adm1266_register_types(void)
{
type_register_static(&adm1266_info);
}
type_init(adm1266_register_types)

1
hw/sensor/meson.build
View File

@ -2,6 +2,7 @@ system_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c'))
system_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c'))
system_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c'))
system_ss.add(when: 'CONFIG_EMC141X', if_true: files('emc141x.c'))
system_ss.add(when: 'CONFIG_ADM1266', if_true: files('adm1266.c'))
system_ss.add(when: 'CONFIG_ADM1272', if_true: files('adm1272.c'))
system_ss.add(when: 'CONFIG_MAX34451', if_true: files('max34451.c'))
system_ss.add(when: 'CONFIG_LSM303DLHC_MAG', if_true: files('lsm303dlhc_mag.c'))

3
include/exec/cpu-common.h
View File

@ -45,9 +45,6 @@ void cpu_list_lock(void);
void cpu_list_unlock(void);
unsigned int cpu_list_generation_id_get(void);
void tcg_flush_softmmu_tlb(CPUState *cs);
void tcg_flush_jmp_cache(CPUState *cs);
void tcg_iommu_init_notifier_list(CPUState *cpu);
void tcg_iommu_free_notifier_list(CPUState *cpu);

2
include/exec/tb-flush.h
View File

@ -23,4 +23,6 @@
*/
void tb_flush(CPUState *cs);
void tcg_flush_jmp_cache(CPUState *cs);
#endif /* _TB_FLUSH_H_ */

20
include/hw/core/cpu.h
View File

@ -102,7 +102,7 @@ struct SysemuCPUOps;
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
* instantiatable CPU type.
* instantiatable CPU type.
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
@ -408,7 +408,7 @@ struct qemu_work_item;
* See TranslationBlock::TCG CF_CLUSTER_MASK.
* @tcg_cflags: Pre-computed cflags for this cpu.
* @nr_cores: Number of cores within this CPU package.
* @nr_threads: Number of threads within this CPU.
* @nr_threads: Number of threads within this CPU core.
* @running: #true if CPU is currently running (lockless).
* @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
* valid under cpu_list_lock.
@ -586,13 +586,13 @@ static inline CPUArchState *cpu_env(CPUState *cpu)
}
typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
extern CPUTailQ cpus;
extern CPUTailQ cpus_queue;
#define first_cpu QTAILQ_FIRST_RCU(&cpus)
#define first_cpu QTAILQ_FIRST_RCU(&cpus_queue)
#define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node)
#define CPU_FOREACH_SAFE(cpu, next_cpu) \
QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu)
extern __thread CPUState *current_cpu;
@ -772,9 +772,10 @@ void cpu_reset(CPUState *cpu);
* @typename: The CPU base type.
* @cpu_model: The model string without any parameters.
*
* Looks up a CPU #ObjectClass matching name @cpu_model.
* Looks up a concrete CPU #ObjectClass matching name @cpu_model.
*
* Returns: A #CPUClass or %NULL if not matching class is found.
* Returns: A concrete #CPUClass or %NULL if no matching class is found
* or if the matching class is abstract.
*/
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
@ -1151,8 +1152,9 @@ G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...)
/* $(top_srcdir)/cpu.c */
void cpu_class_init_props(DeviceClass *dc);
void cpu_exec_initfn(CPUState *cpu);
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
bool cpu_exec_realizefn(CPUState *cpu, Error **errp);
void cpu_exec_unrealizefn(CPUState *cpu);
void cpu_exec_reset_hold(CPUState *cpu);
/**
* target_words_bigendian:

17
include/hw/i2c/pmbus_device.h
View File

@ -243,6 +243,7 @@ OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass,
#define PB_HAS_VIN_RATING BIT_ULL(13)
#define PB_HAS_VOUT_RATING BIT_ULL(14)
#define PB_HAS_VOUT_MODE BIT_ULL(15)
#define PB_HAS_VCAP BIT_ULL(16)
#define PB_HAS_IOUT BIT_ULL(21)
#define PB_HAS_IIN BIT_ULL(22)
#define PB_HAS_IOUT_RATING BIT_ULL(23)
@ -258,6 +259,7 @@ OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass,
#define PB_HAS_TEMP2 BIT_ULL(41)
#define PB_HAS_TEMP3 BIT_ULL(42)
#define PB_HAS_TEMP_RATING BIT_ULL(43)
#define PB_HAS_FAN BIT_ULL(44)
#define PB_HAS_MFR_INFO BIT_ULL(50)
#define PB_HAS_STATUS_MFR_SPECIFIC BIT_ULL(51)
@ -444,6 +446,14 @@ typedef struct PMBusCoefficients {
int32_t R; /* exponent */
} PMBusCoefficients;
/**
* VOUT_Mode bit fields
*/
typedef struct PMBusVoutMode {
uint8_t mode:3;
int8_t exp:5;
} PMBusVoutMode;
/**
* Convert sensor values to direct mode format
*
@ -501,6 +511,13 @@ void pmbus_send64(PMBusDevice *state, uint64_t data);
*/
void pmbus_send_string(PMBusDevice *state, const char *data);
/**
* @brief Receive data sent with Block Write.
* @param dest - memory with enough capacity to receive the write
* @param len - the capacity of dest
*/
uint8_t pmbus_receive_block(PMBusDevice *pmdev, uint8_t *dest, size_t len);
/**
* @brief Receive data over PMBus
* These methods help track how much data is being received over PMBus

33
include/hw/i386/topology.h
View File

@ -24,7 +24,8 @@
#ifndef HW_I386_TOPOLOGY_H
#define HW_I386_TOPOLOGY_H
/* This file implements the APIC-ID-based CPU topology enumeration logic,
/*
* This file implements the APIC-ID-based CPU topology enumeration logic,
* documented at the following document:
* Intel® 64 Architecture Processor Topology Enumeration
* http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
@ -41,7 +42,8 @@
#include "qemu/bitops.h"
/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
/*
* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
*/
typedef uint32_t apic_id_t;
@ -58,8 +60,7 @@ typedef struct X86CPUTopoInfo {
unsigned threads_per_core;
} X86CPUTopoInfo;
/* Return the bit width needed for 'count' IDs
*/
/* Return the bit width needed for 'count' IDs */
static unsigned apicid_bitwidth_for_count(unsigned count)
{
g_assert(count >= 1);
@ -67,15 +68,13 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
return count ? 32 - clz32(count) : 0;
}
/* Bit width of the SMT_ID (thread ID) field on the APIC ID
*/
/* Bit width of the SMT_ID (thread ID) field on the APIC ID */
static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
{
return apicid_bitwidth_for_count(topo_info->threads_per_core);
}
/* Bit width of the Core_ID field
*/
/* Bit width of the Core_ID field */
static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
{
return apicid_bitwidth_for_count(topo_info->cores_per_die);
@ -87,8 +86,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
/* Bit offset of the Core_ID field
*/
/* Bit offset of the Core_ID field */
static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
{
return apicid_smt_width(topo_info);
@ -100,14 +98,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
}
/* Bit offset of the Pkg_ID (socket ID) field
*/
/* Bit offset of the Pkg_ID (socket ID) field */
static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
{
return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
/*
* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
@ -120,7 +118,8 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
topo_ids->smt_id;
}
/* Calculate thread/core/package IDs for a specific topology,
/*
* Calculate thread/core/package IDs for a specific topology,
* based on (contiguous) CPU index
*/
static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
@ -137,7 +136,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
topo_ids->smt_id = cpu_index % nr_threads;
}
/* Calculate thread/core/package IDs for a specific topology,
/*
* Calculate thread/core/package IDs for a specific topology,
* based on APIC ID
*/
static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
@ -155,7 +155,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
}
/* Make APIC ID for the CPU 'cpu_index'
/*
* Make APIC ID for the CPU 'cpu_index'
*
* 'cpu_index' is a sequential, contiguous ID for the CPU.
*/

2
include/hw/loader.h
View File

@ -272,7 +272,7 @@ void pstrcpy_targphys(const char *name,
ssize_t rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex,
bool option_rom, MemoryRegion *mr, AddressSpace *as);
bool has_option_rom, MemoryRegion *mr, AddressSpace *as);
MemoryRegion *rom_add_blob(const char *name, const void *blob, size_t len,
size_t max_len, hwaddr addr,
const char *fw_file_name,

2
include/hw/ppc/ppc.h
View File

@ -1,7 +1,7 @@
#ifndef HW_PPC_H
#define HW_PPC_H
#include "target/ppc/cpu-qom.h"
#include "target/ppc/cpu.h"
void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
PowerPCCPU *ppc_get_vcpu_by_pir(int pir);

2
include/hw/s390x/css.h
View File

@ -233,7 +233,7 @@ typedef enum {
} CssIoAdapterType;
void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode);
uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
uint8_t flags, Error **errp);

5
include/hw/s390x/sclp.h
View File

@ -227,8 +227,7 @@ static inline int sccb_data_len(SCCB *sccb)
void s390_sclp_init(void);
void sclp_service_interrupt(uint32_t sccb);
void raise_irq_cpu_hotplug(void);
int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb,
uint32_t code);
int sclp_service_call(S390CPU *cpu, uint64_t sccb, uint32_t code);
int sclp_service_call_protected(S390CPU *cpu, uint64_t sccb, uint32_t code);
#endif

1
include/sysemu/accel-ops.h
View File

@ -30,6 +30,7 @@ struct AccelOpsClass {
void (*ops_init)(AccelOpsClass *ops);
bool (*cpus_are_resettable)(void);
void (*cpu_reset_hold)(CPUState *cpu);
void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */
void (*kick_vcpu_thread)(CPUState *cpu);

1
include/sysemu/kvm.h
View File

@ -521,7 +521,6 @@ int kvm_set_one_reg(CPUState *cs, uint64_t id, void *source);
* Returns: 0 on success, or a negative errno on failure.
*/
int kvm_get_one_reg(CPUState *cs, uint64_t id, void *target);
struct ppc_radix_page_info *kvm_get_radix_page_info(void);
/* Notify resamplefd for EOI of specific interrupts. */
void kvm_resample_fd_notify(int gsi);

2
linux-user/main.c
View File

@ -156,7 +156,7 @@ void fork_end(int child)
Discard information about the parent threads. */
CPU_FOREACH_SAFE(cpu, next_cpu) {
if (cpu != thread_cpu) {
QTAILQ_REMOVE_RCU(&cpus, cpu, node);
QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node);
}
}
qemu_init_cpu_list();

1
plugins/core.c
View File

@ -21,7 +21,6 @@
#include "qemu/xxhash.h"
#include "qemu/rcu.h"
#include "hw/core/cpu.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/tb-flush.h"

9
system/cpus.c
View File

@ -201,6 +201,13 @@ bool cpus_are_resettable(void)
return true;
}
void cpu_exec_reset_hold(CPUState *cpu)
{
if (cpus_accel->cpu_reset_hold) {
cpus_accel->cpu_reset_hold(cpu);
}
}
int64_t cpus_get_virtual_clock(void)
{
/*
@ -624,7 +631,7 @@ void qemu_init_vcpu(CPUState *cpu)
{
MachineState *ms = MACHINE(qdev_get_machine());
cpu->nr_cores = ms->smp.cores;
cpu->nr_cores = machine_topo_get_cores_per_socket(ms);
cpu->nr_threads = ms->smp.threads;
cpu->stopped = true;
cpu->random_seed = qemu_guest_random_seed_thread_part1();

5
system/vl.c
View File

@ -194,7 +194,7 @@ static int default_sdcard = 1;
static int default_vga = 1;
static int default_net = 1;
static struct {
static const struct {
const char *driver;
int *flag;
} default_list[] = {
@ -1539,7 +1539,8 @@ static gint machine_class_cmp(gconstpointer a, gconstpointer b)
static void machine_help_func(const QDict *qdict)
{
GSList *machines, *el;
g_autoptr(GSList) machines = NULL;
GSList *el;
const char *type = qdict_get_try_str(qdict, "type");
machines = object_class_get_list(TYPE_MACHINE, false);

21
target/alpha/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU Alpha CPU
* QEMU Alpha CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,27 +21,12 @@
#define QEMU_ALPHA_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_ALPHA_CPU "alpha-cpu"
OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
/**
* AlphaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An Alpha CPU model.
*/
struct AlphaCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
#endif

10
target/alpha/cpu.c
View File

@ -126,8 +126,7 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
int i;
oc = object_class_by_name(cpu_model);
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL &&
!object_class_is_abstract(oc)) {
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) {
return oc;
}
@ -142,13 +141,10 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && object_class_is_abstract(oc)) {
oc = NULL;
}
/* TODO: remove match everything nonsense */
/* Default to ev67; no reason not to emulate insns by default. */
if (!oc) {
if (!oc || object_class_is_abstract(oc)) {
/* Default to ev67; no reason not to emulate insns by default. */
oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
}

17
target/alpha/cpu.h
View File

@ -259,9 +259,7 @@ typedef struct CPUArchState {
* An Alpha CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUAlphaState env;
@ -269,6 +267,19 @@ struct ArchCPU {
QEMUTimer *alarm_timer;
};
/**
* AlphaCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An Alpha CPU model.
*/
struct AlphaCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_alpha_cpu;
@ -428,8 +439,6 @@ enum {
void alpha_translate_init(void);
#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
void alpha_cpu_list(void);

61
target/arm/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU ARM CPU
* QEMU ARM CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,7 +21,6 @@
#define QEMU_ARM_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_ARM_CPU "arm-cpu"
@ -29,67 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;
void arm_cpu_register(const ARMCPUInfo *info);
void aarch64_cpu_register(const ARMCPUInfo *info);
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An ARM CPU model.
*/
struct ARMCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
const ARMCPUInfo *info;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define TYPE_AARCH64_CPU "aarch64-cpu"
typedef struct AArch64CPUClass AArch64CPUClass;
DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
TYPE_AARCH64_CPU)
struct AArch64CPUClass {
/*< private >*/
ARMCPUClass parent_class;
/*< public >*/
};
void register_cp_regs_for_features(ARMCPU *cpu);
void init_cpreg_list(ARMCPU *cpu);
/* Callback functions for the generic timer's timers. */
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
void arm_gt_stimer_cb(void *opaque);
void arm_gt_hvtimer_cb(void *opaque);
#define ARM_AFF0_SHIFT 0
#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
#define ARM_AFF1_SHIFT 8
#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
#define ARM_AFF2_SHIFT 16
#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
#define ARM_AFF3_SHIFT 32
#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
#define ARM64_AFFINITY_MASK \
(ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
#endif

3
target/arm/cpu.c
View File

@ -2401,8 +2401,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
oc = object_class_by_name(typename);
g_strfreev(cpuname);
g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
object_class_is_abstract(oc)) {
if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU)) {
return NULL;
}
return oc;

49
target/arm/cpu.h
View File

@ -852,9 +852,7 @@ typedef struct {
* An ARM CPU core.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUARMState env;
@ -1118,11 +1116,58 @@ struct ArchCPU {
uint64_t gt_cntfrq_hz;
};
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An ARM CPU model.
*/
struct ARMCPUClass {
CPUClass parent_class;
const ARMCPUInfo *info;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
struct AArch64CPUClass {
ARMCPUClass parent_class;
};
/* Callback functions for the generic timer's timers. */
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
void arm_gt_stimer_cb(void *opaque);
void arm_gt_hvtimer_cb(void *opaque);
unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
void arm_cpu_post_init(Object *obj);
#define ARM_AFF0_SHIFT 0
#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
#define ARM_AFF1_SHIFT 8
#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
#define ARM_AFF2_SHIFT 16
#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
#define ARM_AFF3_SHIFT 32
#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
#define ARM64_AFFINITY_MASK \
(ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
#ifndef CONFIG_USER_ONLY

6
target/arm/internals.h
View File

@ -183,6 +183,12 @@ static inline int r14_bank_number(int mode)
return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
}
void arm_cpu_register(const ARMCPUInfo *info);
void aarch64_cpu_register(const ARMCPUInfo *info);
void register_cp_regs_for_features(ARMCPU *cpu);
void init_cpreg_list(ARMCPU *cpu);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);

20
target/avr/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU AVR CPU
* QEMU AVR CPU QOM header (target agnostic)
*
* Copyright (c) 2016-2020 Michael Rolnik
*
@ -22,26 +22,12 @@
#define TARGET_AVR_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_AVR_CPU "avr-cpu"
OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
/**
* AVRCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A AVR CPU model.
*/
struct AVRCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
#endif /* TARGET_AVR_CPU_QOM_H */

3
target/avr/cpu.c
View File

@ -157,8 +157,7 @@ static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
ObjectClass *oc;
oc = object_class_by_name(cpu_model);
if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
object_class_is_abstract(oc)) {
if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL) {
oc = NULL;
}
return oc;

18
target/avr/cpu.h
View File

@ -28,8 +28,6 @@
#error "AVR 8-bit does not support user mode"
#endif
#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
#define TCG_GUEST_DEFAULT_MO 0
@ -144,13 +142,25 @@ typedef struct CPUArchState {
* A AVR CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUAVRState env;
};
/**
* AVRCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A AVR CPU model.
*/
struct AVRCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
extern const struct VMStateDescription vms_avr_cpu;
void avr_cpu_do_interrupt(CPUState *cpu);

24
target/cris/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU CRIS CPU
* QEMU CRIS CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,30 +21,12 @@
#define QEMU_CRIS_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_CRIS_CPU "cris-cpu"
OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
/**
* CRISCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @vr: Version Register value.
*
* A CRIS CPU model.
*/
struct CRISCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t vr;
};
#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
#endif

3
target/cris/cpu.c
View File

@ -95,8 +95,7 @@ static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
object_class_is_abstract(oc))) {
if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_CRIS_CPU)) {
oc = NULL;
}
return oc;

20
target/cris/cpu.h
View File

@ -174,13 +174,27 @@ typedef struct CPUArchState {
* A CRIS CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUCRISState env;
};
/**
* CRISCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
* @vr: Version Register value.
*
* A CRIS CPU model.
*/
struct CRISCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t vr;
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_cris_cpu;
@ -242,8 +256,6 @@ enum {
/* CRIS uses 8k pages. */
#define MMAP_SHIFT TARGET_PAGE_BITS
#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
/* MMU modes definitions */

27
target/hexagon/cpu-qom.h Normal file
View File

@ -0,0 +1,27 @@
/*
* QEMU Hexagon CPU QOM header (target agnostic)
*
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef QEMU_HEXAGON_CPU_QOM_H
#define QEMU_HEXAGON_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_HEXAGON_CPU "hexagon-cpu"
#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
#endif

3
target/hexagon/cpu.c
View File

@ -63,8 +63,7 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
oc = object_class_by_name(typename);
g_strfreev(cpuname);
g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) ||
object_class_is_abstract(oc)) {
if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU)) {
return NULL;
}
return oc;

20
target/hexagon/cpu.h
View File

@ -20,11 +20,10 @@
#include "fpu/softfloat-types.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
#include "mmvec/mmvec.h"
#include "qom/object.h"
#include "hw/core/cpu.h"
#include "hw/registerfields.h"
#define NUM_PREGS 4
@ -36,18 +35,8 @@
#define PRED_WRITES_MAX 5 /* 4 insns + endloop */
#define VSTORES_MAX 2
#define TYPE_HEXAGON_CPU "hexagon-cpu"
#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
void hexagon_cpu_list(void);
#define cpu_list hexagon_cpu_list
@ -127,20 +116,15 @@ typedef struct CPUArchState {
VTCMStoreLog vtcm_log;
} CPUHexagonState;
OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
typedef struct HexagonCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
} HexagonCPUClass;
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUHexagonState env;

20
target/hppa/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU HPPA CPU
* QEMU HPPA CPU QOM header (target agnostic)
*
* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
*
@ -21,28 +21,10 @@
#define QEMU_HPPA_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_HPPA_CPU "hppa-cpu"
#define TYPE_HPPA64_CPU "hppa64-cpu"
OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
/**
* HPPACPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An HPPA CPU model.
*/
struct HPPACPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
#endif

16
target/hppa/cpu.h
View File

@ -247,14 +247,26 @@ typedef struct CPUArchState {
* An HPPA CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUHPPAState env;
QEMUTimer *alarm_timer;
};
/**
* HPPACPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An HPPA CPU model.
*/
struct HPPACPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
DeviceReset parent_reset;
};
#include "exec/cpu-all.h"
static inline bool hppa_is_pa20(CPUHPPAState *env)

42
target/i386/cpu-qom.h
View File

@ -21,8 +21,6 @@
#define QEMU_I386_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qemu/notify.h"
#include "qom/object.h"
#ifdef TARGET_X86_64
#define TYPE_X86_CPU "x86_64-cpu"
@ -32,43 +30,7 @@
OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
typedef struct X86CPUModel X86CPUModel;
/**
* X86CPUClass:
* @cpu_def: CPU model definition
* @host_cpuid_required: Whether CPU model requires cpuid from host.
* @ordering: Ordering on the "-cpu help" CPU model list.
* @migration_safe: See CpuDefinitionInfo::migration_safe
* @static_model: See CpuDefinitionInfo::static
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An x86 CPU model or family.
*/
struct X86CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
/* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults.
*/
X86CPUModel *model;
bool host_cpuid_required;
int ordering;
bool migration_safe;
bool static_model;
/* Optional description of CPU model.
* If unavailable, cpu_def->model_id is used */
const char *model_description;
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
};
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#endif

9
target/i386/cpu.c
View File

@ -6019,7 +6019,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
X86CPUTopoInfo topo_info;
topo_info.dies_per_pkg = env->nr_dies;
topo_info.cores_per_die = cs->nr_cores;
topo_info.cores_per_die = cs->nr_cores / env->nr_dies;
topo_info.threads_per_core = cs->nr_threads;
/* Calculate & apply limits for different index ranges */
@ -6095,8 +6095,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*/
if (*eax & 31) {
int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
int vcpus_per_socket = env->nr_dies * cs->nr_cores *
cs->nr_threads;
int vcpus_per_socket = cs->nr_cores * cs->nr_threads;
if (cs->nr_cores > 1) {
*eax &= ~0xFC000000;
*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
@ -6273,12 +6272,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
case 1:
*eax = apicid_die_offset(&topo_info);
*ebx = cs->nr_cores * cs->nr_threads;
*ebx = topo_info.cores_per_die * topo_info.threads_per_core;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
*eax = apicid_pkg_offset(&topo_info);
*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
default:

43
target/i386/cpu.h
View File

@ -1882,6 +1882,7 @@ typedef struct CPUArchState {
TPRAccess tpr_access_type;
/* Number of dies within this CPU package. */
unsigned nr_dies;
} CPUX86State;
@ -1897,9 +1898,7 @@ struct kvm_msrs;
* An x86 CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUX86State env;
VMChangeStateEntry *vmsentry;
@ -2039,6 +2038,44 @@ struct ArchCPU {
bool xen_vapic;
};
typedef struct X86CPUModel X86CPUModel;
/**
* X86CPUClass:
* @cpu_def: CPU model definition
* @host_cpuid_required: Whether CPU model requires cpuid from host.
* @ordering: Ordering on the "-cpu help" CPU model list.
* @migration_safe: See CpuDefinitionInfo::migration_safe
* @static_model: See CpuDefinitionInfo::static
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* An x86 CPU model or family.
*/
struct X86CPUClass {
CPUClass parent_class;
/*
* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults.
*/
X86CPUModel *model;
bool host_cpuid_required;
int ordering;
bool migration_safe;
bool static_model;
/*
* Optional description of CPU model.
* If unavailable, cpu_def->model_id is used.
*/
const char *model_description;
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_x86_cpu;
@ -2241,8 +2278,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_X86_CPU
#ifdef TARGET_X86_64

4
target/i386/hvf/hvf.c
View File

@ -591,9 +591,9 @@ int hvf_vcpu_exec(CPUState *cpu)
{
load_regs(cpu);
if (exit_reason == EXIT_REASON_RDMSR) {
simulate_rdmsr(cpu);
simulate_rdmsr(env);
} else {
simulate_wrmsr(cpu);
simulate_wrmsr(env);
}
env->eip += ins_len;
store_regs(cpu);

111
target/i386/hvf/x86_emu.c
View File

@ -45,7 +45,7 @@
#include "vmcs.h"
#include "vmx.h"
void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
void hvf_handle_io(CPUState *cs, uint16_t port, void *data,
int direction, int size, uint32_t count);
#define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
@ -663,35 +663,34 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
void simulate_rdmsr(struct CPUState *cpu)
void simulate_rdmsr(CPUX86State *env)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
switch (msr) {
case MSR_IA32_TSC:
val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET);
val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
break;
case MSR_IA32_APICBASE:
val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
val = cpu_get_apic_base(cpu->apic_state);
break;
case MSR_IA32_UCODE_REV:
val = x86_cpu->ucode_rev;
val = cpu->ucode_rev;
break;
case MSR_EFER:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER);
val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
break;
case MSR_FSBASE:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE);
val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE);
break;
case MSR_GSBASE:
val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE);
val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE);
break;
case MSR_KERNELGSBASE:
val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE);
val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE);
break;
case MSR_STAR:
abort();
@ -746,7 +745,7 @@ void simulate_rdmsr(struct CPUState *cpu)
val = env->mtrr_deftype;
break;
case MSR_CORE_THREAD_COUNT:
val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
break;
default:
@ -761,14 +760,14 @@ void simulate_rdmsr(struct CPUState *cpu)
static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
{
simulate_rdmsr(env_cpu(env));
simulate_rdmsr(env);
env->eip += decode->len;
}
void simulate_wrmsr(struct CPUState *cpu)
void simulate_wrmsr(CPUX86State *env)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@ -776,16 +775,16 @@ void simulate_wrmsr(struct CPUState *cpu)
case MSR_IA32_TSC:
break;
case MSR_IA32_APICBASE:
cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
cpu_set_apic_base(cpu->apic_state, data);
break;
case MSR_FSBASE:
wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data);
wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
break;
case MSR_GSBASE:
wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data);
wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data);
break;
case MSR_KERNELGSBASE:
wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data);
wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data);
break;
case MSR_STAR:
abort();
@ -797,10 +796,10 @@ void simulate_wrmsr(struct CPUState *cpu)
abort();
break;
case MSR_EFER:
/*printf("new efer %llx\n", EFER(cpu));*/
wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data);
/*printf("new efer %llx\n", EFER(cs));*/
wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data);
if (data & MSR_EFER_NXE) {
hv_vcpu_invalidate_tlb(cpu->accel->fd);
hv_vcpu_invalidate_tlb(cs->accel->fd);
}
break;
case MSR_MTRRphysBase(0):
@ -849,14 +848,14 @@ void simulate_wrmsr(struct CPUState *cpu)
/* Related to support known hypervisor interface */
/* if (g_hypervisor_iface)
g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
g_hypervisor_iface->wrmsr_handler(cs, msr, data);
printf("write msr %llx\n", RCX(cpu));*/
printf("write msr %llx\n", RCX(cs));*/
}
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
{
simulate_wrmsr(env_cpu(env));
simulate_wrmsr(env);
env->eip += decode->len;
}
@ -1418,56 +1417,56 @@ static void init_cmd_handler()
}
}
void load_regs(struct CPUState *cpu)
void load_regs(CPUState *cs)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
int i = 0;
RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX);
RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX);
RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX);
RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX);
RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI);
RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI);
RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP);
RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP);
RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX);
RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX);
RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX);
RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI);
RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI);
RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP);
RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP);
for (i = 8; i < 16; i++) {
RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i);
RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i);
}
env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS);
env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
rflags_to_lflags(env);
env->eip = rreg(cpu->accel->fd, HV_X86_RIP);
env->eip = rreg(cs->accel->fd, HV_X86_RIP);
}
void store_regs(struct CPUState *cpu)
void store_regs(CPUState *cs)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
int i = 0;
wreg(cpu->accel->fd, HV_X86_RAX, RAX(env));
wreg(cpu->accel->fd, HV_X86_RBX, RBX(env));
wreg(cpu->accel->fd, HV_X86_RCX, RCX(env));
wreg(cpu->accel->fd, HV_X86_RDX, RDX(env));
wreg(cpu->accel->fd, HV_X86_RSI, RSI(env));
wreg(cpu->accel->fd, HV_X86_RDI, RDI(env));
wreg(cpu->accel->fd, HV_X86_RBP, RBP(env));
wreg(cpu->accel->fd, HV_X86_RSP, RSP(env));
wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
wreg(cs->accel->fd, HV_X86_RBX, RBX(env));
wreg(cs->accel->fd, HV_X86_RCX, RCX(env));
wreg(cs->accel->fd, HV_X86_RDX, RDX(env));
wreg(cs->accel->fd, HV_X86_RSI, RSI(env));
wreg(cs->accel->fd, HV_X86_RDI, RDI(env));
wreg(cs->accel->fd, HV_X86_RBP, RBP(env));
wreg(cs->accel->fd, HV_X86_RSP, RSP(env));
for (i = 8; i < 16; i++) {
wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i));
wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i));
}
lflags_to_rflags(env);
wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags);
macvm_set_rip(cpu, env->eip);
wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
macvm_set_rip(cs, env->eip);
}
bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
{
/*if (hvf_vcpu_id(cpu))
printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip,
/*if (hvf_vcpu_id(cs))
printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cs), env->eip,
decode_cmd_to_string(ins->cmd));*/
if (!_cmd_handler[ins->cmd].handler) {

4
target/i386/hvf/x86_emu.h
View File

@ -29,8 +29,8 @@ bool exec_instruction(CPUX86State *env, struct x86_decode *ins);
void load_regs(struct CPUState *cpu);
void store_regs(struct CPUState *cpu);
void simulate_rdmsr(struct CPUState *cpu);
void simulate_wrmsr(struct CPUState *cpu);
void simulate_rdmsr(CPUX86State *env);
void simulate_wrmsr(CPUX86State *env);
target_ulong read_reg(CPUX86State *env, int reg, int size);
void write_reg(CPUX86State *env, int reg, target_ulong val, int size);

1
target/i386/kvm/kvm-cpu.c
View File

@ -37,6 +37,7 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
* -> cpu_exec_realizefn():
* -> accel_cpu_common_realize()
* kvm_cpu_realizefn() -> host_cpu_realizefn()
* -> cpu_common_realizefn()
* -> check/update ucode_rev, phys_bits, mwait
*/
if (cpu->max_features) {

5
target/i386/monitor.c
View File

@ -28,6 +28,7 @@
#include "monitor/hmp-target.h"
#include "monitor/hmp.h"
#include "qapi/qmp/qdict.h"
#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc-target.h"
@ -654,7 +655,11 @@ void hmp_info_local_apic(Monitor *mon, const QDict *qdict)
if (qdict_haskey(qdict, "apic-id")) {
int id = qdict_get_try_int(qdict, "apic-id", 0);
cs = cpu_by_arch_id(id);
if (cs) {
cpu_synchronize_state(cs);
}
} else {
cs = mon_get_cpu(mon);
}

23
target/loongarch/cpu-qom.h Normal file
View File

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QEMU LoongArch CPU QOM header (target agnostic)
*
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
#ifndef LOONGARCH_CPU_QOM_H
#define LOONGARCH_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
LOONGARCH_CPU)
#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
#endif

3
target/loongarch/cpu.c
View File

@ -721,8 +721,7 @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
}
}
if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU)
&& !object_class_is_abstract(oc)) {
if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU)) {
return oc;
}
return NULL;

14
target/loongarch/cpu.h
View File

@ -17,6 +17,7 @@
#include "exec/memory.h"
#endif
#include "cpu-csr.h"
#include "cpu-qom.h"
#define IOCSRF_TEMP 0
#define IOCSRF_NODECNT 1
@ -371,9 +372,7 @@ typedef struct CPUArchState {
* A LoongArch CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPULoongArchState env;
QEMUTimer timer;
@ -383,13 +382,6 @@ struct ArchCPU {
const char *dtb_compatible;
};
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
LOONGARCH_CPU)
/**
* LoongArchCPUClass:
* @parent_realize: The parent class' realize handler.
@ -398,9 +390,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
* A LoongArch CPU model.
*/
struct LoongArchCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
@ -482,8 +472,6 @@ void loongarch_cpu_list(void);
#include "exec/cpu-all.h"
#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
void loongarch_cpu_post_init(Object *obj);

21
target/m68k/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU Motorola 68k CPU
* QEMU Motorola 68k CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,27 +21,12 @@
#define QEMU_M68K_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_M68K_CPU "m68k-cpu"
OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
/*
* M68kCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A Motorola 68k CPU model.
*/
struct M68kCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
#endif

3
target/m68k/cpu.c
View File

@ -111,8 +111,7 @@ static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(M68K_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && (object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL ||
object_class_is_abstract(oc))) {
if (oc != NULL && object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL) {
return NULL;
}
return oc;

17
target/m68k/cpu.h
View File

@ -164,13 +164,24 @@ typedef struct CPUArchState {
* A Motorola 68k CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUM68KState env;
};
/*
* M68kCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A Motorola 68k CPU model.
*/
struct M68kCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#ifndef CONFIG_USER_ONLY
void m68k_cpu_do_interrupt(CPUState *cpu);
@ -563,8 +574,6 @@ enum {
ACCESS_DATA = 0x20, /* Data load/store access */
};
#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_M68K_CPU
#define cpu_list m68k_cpu_list

20
target/microblaze/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU MicroBlaze CPU
* QEMU MicroBlaze CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,27 +21,9 @@
#define QEMU_MICROBLAZE_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
/**
* MicroBlazeCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MicroBlaze CPU model.
*/
struct MicroBlazeCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#endif

15
target/microblaze/cpu.h
View File

@ -343,9 +343,7 @@ typedef struct {
* A MicroBlaze CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUMBState env;
@ -357,6 +355,19 @@ struct ArchCPU {
MicroBlazeCPUConfig cfg;
};
/**
* MicroBlazeCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MicroBlaze CPU model.
*/
struct MicroBlazeCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#ifndef CONFIG_USER_ONLY
void mb_cpu_do_interrupt(CPUState *cs);

23
target/mips/cpu-qom.h
View File

@ -21,7 +21,6 @@
#define QEMU_MIPS_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#ifdef TARGET_MIPS64
#define TYPE_MIPS_CPU "mips64-cpu"
@ -31,25 +30,7 @@
OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
/**
* MIPSCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MIPS CPU model.
*/
struct MIPSCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
const struct mips_def_t *cpu_def;
/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
bool no_data_aborts;
};
#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
#endif

21
target/mips/cpu.h
View File

@ -1209,9 +1209,7 @@ typedef struct CPUArchState {
* A MIPS CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUMIPSState env;
@ -1219,6 +1217,23 @@ struct ArchCPU {
Clock *count_div; /* Divider for CP0_Count clock */
};
/**
* MIPSCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A MIPS CPU model.
*/
struct MIPSCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
ResettablePhases parent_phases;
const struct mips_def_t *cpu_def;
/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
bool no_data_aborts;
};
void mips_cpu_list(void);
@ -1303,8 +1318,6 @@ enum {
*/
#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
bool cpu_type_supports_cps_smp(const char *cpu_type);

4
target/mips/tcg/msa.decode
View File

@ -31,8 +31,8 @@
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:s16 &msa_bz
@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n
@elm ...... .......... ws:5 wd:5 ...... &msa_elm
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0

2
target/mips/tcg/tx79.decode
View File

@ -24,7 +24,7 @@
@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0
@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0
@ldst ...... base:5 rt:5 offset:16 &i
@ldst ...... base:5 rt:5 offset:s16 &i
###########################################################################

18
target/nios2/cpu-qom.h Normal file
View File

@ -0,0 +1,18 @@
/*
* QEMU Nios II CPU QOM header (target agnostic)
*
* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#ifndef QEMU_NIOS2_CPU_QOM_H
#define QEMU_NIOS2_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_NIOS2_CPU "nios2-cpu"
OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
#endif

16
target/nios2/cpu.c
View File

@ -199,14 +199,6 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
Error *local_err = NULL;
#ifndef CONFIG_USER_ONLY
if (cpu->eic_present) {
qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1);
} else {
qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32);
}
#endif
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@ -220,6 +212,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
/* We have reserved storage for cpuid; might as well use it. */
cpu->env.ctrl[CR_CPUID] = cs->cpu_index;
#ifndef CONFIG_USER_ONLY
if (cpu->eic_present) {
qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1);
} else {
qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32);
}
#endif
ncc->parent_realize(dev, errp);
}

11
target/nios2/cpu.h
View File

@ -21,20 +21,15 @@
#ifndef NIOS2_CPU_H
#define NIOS2_CPU_H
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "hw/registerfields.h"
#include "qom/object.h"
typedef struct CPUArchState CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif
#define TYPE_NIOS2_CPU "nios2-cpu"
OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
/**
* Nios2CPUClass:
* @parent_phases: The parent class' reset phase handlers.
@ -42,9 +37,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
* A Nios2 CPU model.
*/
struct Nios2CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
@ -214,9 +207,7 @@ typedef struct {
* A Nios2 CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNios2State env;

21
target/openrisc/cpu-qom.h Normal file
View File

@ -0,0 +1,21 @@
/*
* QEMU OpenRISC CPU QOM header (target agnostic)
*
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#ifndef QEMU_OPENRISC_CPU_QOM_H
#define QEMU_OPENRISC_CPU_QOM_H
#include "hw/core/cpu.h"
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#endif

3
target/openrisc/cpu.c
View File

@ -164,8 +164,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
object_class_is_abstract(oc))) {
if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU)) {
return NULL;
}
return oc;

14
target/openrisc/cpu.h
View File

@ -20,17 +20,12 @@
#ifndef OPENRISC_CPU_H
#define OPENRISC_CPU_H
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TCG_GUEST_DEFAULT_MO (0)
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
/**
* OpenRISCCPUClass:
* @parent_realize: The parent class' realize handler.
@ -39,9 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
* A OpenRISC CPU model.
*/
struct OpenRISCCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
@ -301,14 +294,11 @@ typedef struct CPUArchState {
* A OpenRISC CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUOpenRISCState env;
};
void cpu_openrisc_list(void);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@ -343,8 +333,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu);
void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#endif
#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
#include "exec/cpu-all.h"

164
target/ppc/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU PowerPC CPU
* QEMU PowerPC CPU QOM header (target agnostic)
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -21,7 +21,6 @@
#define QEMU_PPC_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#ifdef TARGET_PPC64
#define TYPE_POWERPC_CPU "powerpc64-cpu"
@ -33,170 +32,9 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
ObjectClass *ppc_cpu_class_by_name(const char *name);
typedef struct CPUArchState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_dcr_t ppc_dcr_t;
/*****************************************************************************/
/* MMU model */
typedef enum powerpc_mmu_t powerpc_mmu_t;
enum powerpc_mmu_t {
POWERPC_MMU_UNKNOWN = 0x00000000,
/* Standard 32 bits PowerPC MMU */
POWERPC_MMU_32B = 0x00000001,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_SOFT_6xx = 0x00000002,
/*
* PowerPC 74xx MMU with software TLB (this has been
* disabled, see git history for more information.
* keywords: tlbld tlbli TLBMISS PTEHI PTELO)
*/
POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x00000004,
/* PowerPC MMU in real mode only */
POWERPC_MMU_REAL = 0x00000006,
/* Freescale MPC8xx MMU model */
POWERPC_MMU_MPC8xx = 0x00000007,
/* BookE MMU model */
POWERPC_MMU_BOOKE = 0x00000008,
/* BookE 2.06 MMU model */
POWERPC_MMU_BOOKE206 = 0x00000009,
#define POWERPC_MMU_64 0x00010000
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
/* Architecture 3.00 variant */
POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
};
static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
{
return mmu_model & POWERPC_MMU_64;
}
/*****************************************************************************/
/* Exception model */
typedef enum powerpc_excp_t powerpc_excp_t;
enum powerpc_excp_t {
POWERPC_EXCP_UNKNOWN = 0,
/* Standard PowerPC exception model */
POWERPC_EXCP_STD,
/* PowerPC 40x exception model */
POWERPC_EXCP_40x,
/* PowerPC 603/604/G2 exception model */
POWERPC_EXCP_6xx,
/* PowerPC 7xx exception model */
POWERPC_EXCP_7xx,
/* PowerPC 74xx exception model */
POWERPC_EXCP_74xx,
/* BookE exception model */
POWERPC_EXCP_BOOKE,
/* PowerPC 970 exception model */
POWERPC_EXCP_970,
/* POWER7 exception model */
POWERPC_EXCP_POWER7,
/* POWER8 exception model */
POWERPC_EXCP_POWER8,
/* POWER9 exception model */
POWERPC_EXCP_POWER9,
/* POWER10 exception model */
POWERPC_EXCP_POWER10,
};
/*****************************************************************************/
/* PM instructions */
typedef enum {
PPC_PM_DOZE,
PPC_PM_NAP,
PPC_PM_SLEEP,
PPC_PM_RVWINKLE,
PPC_PM_STOP,
} powerpc_pm_insn_t;
/*****************************************************************************/
/* Input pins model */
typedef enum powerpc_input_t powerpc_input_t;
enum powerpc_input_t {
PPC_FLAGS_INPUT_UNKNOWN = 0,
/* PowerPC 6xx bus */
PPC_FLAGS_INPUT_6xx,
/* BookE bus */
PPC_FLAGS_INPUT_BookE,
/* PowerPC 405 bus */
PPC_FLAGS_INPUT_405,
/* PowerPC 970 bus */
PPC_FLAGS_INPUT_970,
/* PowerPC POWER7 bus */
PPC_FLAGS_INPUT_POWER7,
/* PowerPC POWER9 bus */
PPC_FLAGS_INPUT_POWER9,
/* Freescale RCPU bus */
PPC_FLAGS_INPUT_RCPU,
};
typedef struct PPCHash64Options PPCHash64Options;
/**
* PowerPCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A PowerPC CPU model.
*/
struct PowerPCCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
void (*parent_parse_features)(const char *type, char *str, Error **errp);
uint32_t pvr;
/*
* If @best is false, match if pcc is in the family of pvr
* Else match only if pcc is the best match for pvr in this family.
*/
bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
uint64_t pcr_mask; /* Available bits in PCR register */
uint64_t pcr_supported; /* Bits for supported PowerISA versions */
uint32_t svr;
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
uint64_t lpcr_mask; /* Available bits in the LPCR */
uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
powerpc_input_t bus_model;
uint32_t flags;
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
#ifndef CONFIG_USER_ONLY
unsigned int gdb_num_sprs;
const char *gdb_spr_xml;
#endif
const PPCHash64Options *hash64_opts;
struct ppc_radix_page_info *radix_page_info;
uint32_t lrg_decr_bits;
int n_host_threads;
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
};
#ifndef CONFIG_USER_ONLY
typedef struct PPCTimebase {
uint64_t guest_timebase;

145
target/ppc/cpu.h
View File

@ -27,6 +27,8 @@
#include "qom/object.h"
#include "hw/registerfields.h"
#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
#define TCG_GUEST_DEFAULT_MO 0
#define TARGET_PAGE_BITS_64K 16
@ -190,6 +192,95 @@ enum {
POWERPC_EXCP_TRAP = 0x40,
};
/* Exception model */
typedef enum powerpc_excp_t {
POWERPC_EXCP_UNKNOWN = 0,
/* Standard PowerPC exception model */
POWERPC_EXCP_STD,
/* PowerPC 40x exception model */
POWERPC_EXCP_40x,
/* PowerPC 603/604/G2 exception model */
POWERPC_EXCP_6xx,
/* PowerPC 7xx exception model */
POWERPC_EXCP_7xx,
/* PowerPC 74xx exception model */
POWERPC_EXCP_74xx,
/* BookE exception model */
POWERPC_EXCP_BOOKE,
/* PowerPC 970 exception model */
POWERPC_EXCP_970,
/* POWER7 exception model */
POWERPC_EXCP_POWER7,
/* POWER8 exception model */
POWERPC_EXCP_POWER8,
/* POWER9 exception model */
POWERPC_EXCP_POWER9,
/* POWER10 exception model */
POWERPC_EXCP_POWER10,
} powerpc_excp_t;
/*****************************************************************************/
/* MMU model */
typedef enum powerpc_mmu_t {
POWERPC_MMU_UNKNOWN = 0x00000000,
/* Standard 32 bits PowerPC MMU */
POWERPC_MMU_32B = 0x00000001,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_SOFT_6xx = 0x00000002,
/*
* PowerPC 74xx MMU with software TLB (this has been
* disabled, see git history for more information.
* keywords: tlbld tlbli TLBMISS PTEHI PTELO)
*/
POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x00000004,
/* PowerPC MMU in real mode only */
POWERPC_MMU_REAL = 0x00000006,
/* Freescale MPC8xx MMU model */
POWERPC_MMU_MPC8xx = 0x00000007,
/* BookE MMU model */
POWERPC_MMU_BOOKE = 0x00000008,
/* BookE 2.06 MMU model */
POWERPC_MMU_BOOKE206 = 0x00000009,
#define POWERPC_MMU_64 0x00010000
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
/* Architecture 3.00 variant */
POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
} powerpc_mmu_t;
static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
{
return mmu_model & POWERPC_MMU_64;
}
/*****************************************************************************/
/* Input pins model */
typedef enum powerpc_input_t {
PPC_FLAGS_INPUT_UNKNOWN = 0,
/* PowerPC 6xx bus */
PPC_FLAGS_INPUT_6xx,
/* BookE bus */
PPC_FLAGS_INPUT_BookE,
/* PowerPC 405 bus */
PPC_FLAGS_INPUT_405,
/* PowerPC 970 bus */
PPC_FLAGS_INPUT_970,
/* PowerPC POWER7 bus */
PPC_FLAGS_INPUT_POWER7,
/* PowerPC POWER9 bus */
PPC_FLAGS_INPUT_POWER9,
/* Freescale RCPU bus */
PPC_FLAGS_INPUT_RCPU,
} powerpc_input_t;
#define PPC_INPUT(env) ((env)->bus_model)
/*****************************************************************************/
@ -198,9 +289,14 @@ typedef struct opc_handler_t opc_handler_t;
/*****************************************************************************/
/* Types used to describe some PowerPC registers etc. */
typedef struct DisasContext DisasContext;
typedef struct ppc_dcr_t ppc_dcr_t;
typedef struct ppc_spr_t ppc_spr_t;
typedef struct ppc_tb_t ppc_tb_t;
typedef union ppc_tlb_t ppc_tlb_t;
typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
typedef struct PPCHash64Options PPCHash64Options;
typedef struct CPUArchState CPUPPCState;
/* SPR access micro-ops generations callbacks */
struct ppc_spr_t {
@ -1313,9 +1409,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
* A PowerPC CPU.
*/
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUPPCState env;
@ -1341,7 +1435,54 @@ struct ArchCPU {
int32_t mig_slb_nr;
};
/**
* PowerPCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A PowerPC CPU model.
*/
struct PowerPCCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
void (*parent_parse_features)(const char *type, char *str, Error **errp);
uint32_t pvr;
/*
* If @best is false, match if pcc is in the family of pvr
* Else match only if pcc is the best match for pvr in this family.
*/
bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
uint64_t pcr_mask; /* Available bits in PCR register */
uint64_t pcr_supported; /* Bits for supported PowerISA versions */
uint32_t svr;
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
uint64_t lpcr_mask; /* Available bits in the LPCR */
uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
powerpc_input_t bus_model;
uint32_t flags;
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
#ifndef CONFIG_USER_ONLY
unsigned int gdb_num_sprs;
const char *gdb_spr_xml;
#endif
const PPCHash64Options *hash64_opts;
struct ppc_radix_page_info *radix_page_info;
uint32_t lrg_decr_bits;
int n_host_threads;
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
};
ObjectClass *ppc_cpu_class_by_name(const char *name);
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);

2
target/ppc/excp_helper.c
View File

@ -3136,7 +3136,7 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
{
CPUState *cs = env_cpu(env);
PowerPCCPU *cpu = POWERPC_CPU(cs);
PowerPCCPU *cpu = env_archcpu(env);
CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
int ttir = rb & PPC_BITMASK(57, 63);

9
target/ppc/internal.h
View File

@ -20,6 +20,15 @@
#include "hw/registerfields.h"
/* PM instructions */
typedef enum {
PPC_PM_DOZE,
PPC_PM_NAP,
PPC_PM_SLEEP,
PPC_PM_RVWINKLE,
PPC_PM_STOP,
} powerpc_pm_insn_t;
#define FUNC_MASK(name, ret_type, size, max_val) \
static inline ret_type name(uint##size##_t start, \
uint##size##_t end) \

19
target/ppc/kvm-stub.c
View File

@ -1,19 +0,0 @@
/*
* QEMU KVM PPC specific function stubs
*
* Copyright Freescale Inc. 2013
*
* Author: Alexander Graf <agraf@suse.de>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/ppc/openpic_kvm.h"
int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
{
return -EINVAL;
}

4
target/ppc/kvm.c
View File

@ -268,7 +268,7 @@ static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
"KVM failed to provide the MMU features it supports");
}
struct ppc_radix_page_info *kvm_get_radix_page_info(void)
static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void)
{
KVMState *s = KVM_STATE(current_accel());
struct ppc_radix_page_info *radix_page_info;
@ -2368,7 +2368,7 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
}
#if defined(TARGET_PPC64)
pcc->radix_page_info = kvm_get_radix_page_info();
pcc->radix_page_info = kvmppc_get_radix_page_info();
if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
/*

4
target/ppc/kvm_ppc.h
View File

@ -13,6 +13,10 @@
#include "exec/hwaddr.h"
#include "cpu.h"
#ifdef CONFIG_USER_ONLY
#error Cannot include kvm_ppc.h from user emulation
#endif
#ifdef CONFIG_KVM
uint32_t kvmppc_get_tbfreq(void);

2
target/ppc/meson.build
View File

@ -30,7 +30,6 @@ gen = [
]
ppc_ss.add(when: 'CONFIG_TCG', if_true: gen)
ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
ppc_system_ss = ss.source_set()
@ -46,6 +45,7 @@ ppc_system_ss.add(when: 'CONFIG_TCG', if_true: files(
), if_false: files(
'tcg-stub.c',
))
ppc_system_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
ppc_system_ss.add(when: 'TARGET_PPC64', if_true: files(
'compat.c',

26
target/riscv/cpu-qom.h
View File

@ -1,5 +1,5 @@
/*
* QEMU RISC-V CPU QOM header
* QEMU RISC-V CPU QOM header (target agnostic)
*
* Copyright (c) 2023 Ventana Micro Systems Inc.
*
@ -20,14 +20,12 @@
#define RISCV_CPU_QOM_H
#include "hw/core/cpu.h"
#include "qom/object.h"
#define TYPE_RISCV_CPU "riscv-cpu"
#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
@ -45,28 +43,6 @@
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
typedef struct CPUArchState CPURISCVState;
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RISCV CPU model.
*/
struct RISCVCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
#endif /* RISCV_CPU_QOM_H */

Some files were not shown because too many files have changed in this diff Show More