cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
parent
801c4c287b
commit
ed2803da58
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@ -297,7 +297,7 @@ int cpu_exec(CPUArchState *env)
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for(;;) {
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for(;;) {
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interrupt_request = cpu->interrupt_request;
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interrupt_request = cpu->interrupt_request;
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if (unlikely(interrupt_request)) {
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if (unlikely(interrupt_request)) {
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if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
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if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
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/* Mask out external interrupts for this step. */
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/* Mask out external interrupts for this step. */
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interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
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interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
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}
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}
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2
cpus.c
2
cpus.c
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@ -1186,7 +1186,7 @@ static void tcg_exec_all(void)
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CPUArchState *env = cpu->env_ptr;
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CPUArchState *env = cpu->env_ptr;
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qemu_clock_enable(vm_clock,
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qemu_clock_enable(vm_clock,
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(env->singlestep_enabled & SSTEP_NOTIMER) == 0);
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(cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
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if (cpu_can_run(cpu)) {
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if (cpu_can_run(cpu)) {
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r = tcg_cpu_exec(env);
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r = tcg_cpu_exec(env);
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10
exec.c
10
exec.c
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@ -588,11 +588,13 @@ void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
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void cpu_single_step(CPUArchState *env, int enabled)
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void cpu_single_step(CPUArchState *env, int enabled)
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{
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{
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#if defined(TARGET_HAS_ICE)
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#if defined(TARGET_HAS_ICE)
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if (env->singlestep_enabled != enabled) {
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CPUState *cpu = ENV_GET_CPU(env);
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env->singlestep_enabled = enabled;
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if (kvm_enabled())
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if (cpu->singlestep_enabled != enabled) {
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cpu->singlestep_enabled = enabled;
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if (kvm_enabled()) {
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kvm_update_guest_debug(env, 0);
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kvm_update_guest_debug(env, 0);
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else {
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} else {
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/* must flush all the translated code to avoid inconsistencies */
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/* must flush all the translated code to avoid inconsistencies */
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/* XXX: only flush what is necessary */
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/* XXX: only flush what is necessary */
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tb_flush(env);
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tb_flush(env);
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@ -170,7 +170,6 @@ typedef struct CPUWatchpoint {
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/* from this point: preserved by CPU reset */ \
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/* from this point: preserved by CPU reset */ \
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/* ice debug support */ \
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/* ice debug support */ \
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QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
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QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
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int singlestep_enabled; \
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\
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\
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QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
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QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
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CPUWatchpoint *watchpoint_hit; \
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CPUWatchpoint *watchpoint_hit; \
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@ -133,6 +133,7 @@ struct kvm_run;
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* @stopped: Indicates the CPU has been artificially stopped.
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* @stopped: Indicates the CPU has been artificially stopped.
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* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
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* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
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* CPU and return to its top level loop.
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* CPU and return to its top level loop.
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* @singlestep_enabled: Flags for single-stepping.
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* @env_ptr: Pointer to subclass-specific CPUArchState field.
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* @env_ptr: Pointer to subclass-specific CPUArchState field.
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* @current_tb: Currently executing TB.
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* @current_tb: Currently executing TB.
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* @next_cpu: Next CPU sharing TB cache.
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* @next_cpu: Next CPU sharing TB cache.
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@ -165,6 +166,7 @@ struct CPUState {
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volatile sig_atomic_t exit_request;
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volatile sig_atomic_t exit_request;
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volatile sig_atomic_t tcg_exit_req;
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volatile sig_atomic_t tcg_exit_req;
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uint32_t interrupt_request;
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uint32_t interrupt_request;
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int singlestep_enabled;
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void *env_ptr; /* CPUArchState */
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void *env_ptr; /* CPUArchState */
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struct TranslationBlock *current_tb;
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struct TranslationBlock *current_tb;
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@ -1890,7 +1890,7 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
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data.dbg.control = reinject_trap;
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data.dbg.control = reinject_trap;
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if (env->singlestep_enabled) {
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if (cpu->singlestep_enabled) {
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data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP;
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data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP;
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}
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}
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kvm_arch_update_guest_debug(cpu, &data.dbg);
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kvm_arch_update_guest_debug(cpu, &data.dbg);
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@ -3388,6 +3388,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
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TranslationBlock *tb,
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TranslationBlock *tb,
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bool search_pc)
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bool search_pc)
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{
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{
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CPUState *cs = CPU(cpu);
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CPUAlphaState *env = &cpu->env;
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CPUAlphaState *env = &cpu->env;
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DisasContext ctx, *ctxp = &ctx;
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DisasContext ctx, *ctxp = &ctx;
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target_ulong pc_start;
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target_ulong pc_start;
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@ -3406,7 +3407,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
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ctx.pc = pc_start;
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ctx.pc = pc_start;
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ctx.mem_idx = cpu_mmu_index(env);
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ctx.mem_idx = cpu_mmu_index(env);
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ctx.implver = env->implver;
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ctx.implver = env->implver;
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ctx.singlestep_enabled = env->singlestep_enabled;
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ctx.singlestep_enabled = cs->singlestep_enabled;
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/* ??? Every TB begins with unset rounding mode, to be initialized on
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/* ??? Every TB begins with unset rounding mode, to be initialized on
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the first fp insn of the TB. Alternately we could define a proper
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the first fp insn of the TB. Alternately we could define a proper
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@ -9911,6 +9911,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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TranslationBlock *tb,
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TranslationBlock *tb,
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bool search_pc)
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bool search_pc)
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{
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{
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CPUState *cs = CPU(cpu);
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CPUARMState *env = &cpu->env;
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CPUARMState *env = &cpu->env;
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DisasContext dc1, *dc = &dc1;
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DisasContext dc1, *dc = &dc1;
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CPUBreakpoint *bp;
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CPUBreakpoint *bp;
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@ -9930,7 +9931,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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dc->is_jmp = DISAS_NEXT;
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dc->is_jmp = DISAS_NEXT;
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dc->pc = pc_start;
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dc->pc = pc_start;
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dc->singlestep_enabled = env->singlestep_enabled;
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->condjmp = 0;
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dc->condjmp = 0;
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dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
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dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
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dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
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dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
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@ -10080,7 +10081,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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* ensures prefetch aborts occur at the right place. */
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* ensures prefetch aborts occur at the right place. */
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num_insns ++;
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num_insns ++;
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} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
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} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
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!env->singlestep_enabled &&
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!cs->singlestep_enabled &&
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!singlestep &&
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!singlestep &&
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dc->pc < next_page_start &&
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dc->pc < next_page_start &&
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num_insns < max_insns);
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num_insns < max_insns);
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@ -10097,7 +10098,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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/* At this stage dc->condjmp will only be set when the skipped
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/* At this stage dc->condjmp will only be set when the skipped
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instruction was a conditional branch or trap, and the PC has
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instruction was a conditional branch or trap, and the PC has
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already been written. */
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already been written. */
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if (unlikely(env->singlestep_enabled)) {
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if (unlikely(cs->singlestep_enabled)) {
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/* Make sure the pc is updated, and raise a debug exception. */
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/* Make sure the pc is updated, and raise a debug exception. */
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if (dc->condjmp) {
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if (dc->condjmp) {
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gen_set_condexec(dc);
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gen_set_condexec(dc);
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@ -3165,6 +3165,7 @@ static inline void
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gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
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gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
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bool search_pc)
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bool search_pc)
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{
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{
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CPUState *cs = CPU(cpu);
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CPUCRISState *env = &cpu->env;
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CPUCRISState *env = &cpu->env;
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uint16_t *gen_opc_end;
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uint16_t *gen_opc_end;
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uint32_t pc_start;
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uint32_t pc_start;
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@ -3197,7 +3198,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
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dc->is_jmp = DISAS_NEXT;
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dc->is_jmp = DISAS_NEXT;
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dc->ppc = pc_start;
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dc->ppc = pc_start;
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dc->pc = pc_start;
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dc->pc = pc_start;
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dc->singlestep_enabled = env->singlestep_enabled;
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->flags_uptodate = 1;
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dc->flags_uptodate = 1;
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dc->flagx_known = 1;
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dc->flagx_known = 1;
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dc->flags_x = tb->flags & X_FLAG;
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dc->flags_x = tb->flags & X_FLAG;
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@ -3337,7 +3338,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
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/* If we are rexecuting a branch due to exceptions on
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/* If we are rexecuting a branch due to exceptions on
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delay slots dont break. */
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delay slots dont break. */
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if (!(tb->pc & 1) && env->singlestep_enabled) {
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if (!(tb->pc & 1) && cs->singlestep_enabled) {
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break;
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break;
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}
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}
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} while (!dc->is_jmp && !dc->cpustate_changed
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} while (!dc->is_jmp && !dc->cpustate_changed
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@ -3370,7 +3371,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
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cris_evaluate_flags(dc);
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cris_evaluate_flags(dc);
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if (unlikely(env->singlestep_enabled)) {
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if (unlikely(cs->singlestep_enabled)) {
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if (dc->is_jmp == DISAS_NEXT) {
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if (dc->is_jmp == DISAS_NEXT) {
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tcg_gen_movi_tl(env_pc, npc);
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tcg_gen_movi_tl(env_pc, npc);
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}
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}
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@ -1594,6 +1594,7 @@ static int kvm_get_vcpu_events(X86CPU *cpu)
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static int kvm_guest_debug_workarounds(X86CPU *cpu)
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static int kvm_guest_debug_workarounds(X86CPU *cpu)
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{
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{
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CPUState *cs = CPU(cpu);
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CPUX86State *env = &cpu->env;
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CPUX86State *env = &cpu->env;
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int ret = 0;
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int ret = 0;
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unsigned long reinject_trap = 0;
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unsigned long reinject_trap = 0;
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@ -1616,7 +1617,7 @@ static int kvm_guest_debug_workarounds(X86CPU *cpu)
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* reinject them via SET_GUEST_DEBUG.
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* reinject them via SET_GUEST_DEBUG.
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*/
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*/
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if (reinject_trap ||
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if (reinject_trap ||
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(!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
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(!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
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ret = kvm_update_guest_debug(env, reinject_trap);
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ret = kvm_update_guest_debug(env, reinject_trap);
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}
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}
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return ret;
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return ret;
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@ -2042,13 +2043,14 @@ static CPUWatchpoint hw_watchpoint;
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static int kvm_handle_debug(X86CPU *cpu,
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static int kvm_handle_debug(X86CPU *cpu,
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struct kvm_debug_exit_arch *arch_info)
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struct kvm_debug_exit_arch *arch_info)
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{
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{
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CPUState *cs = CPU(cpu);
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CPUX86State *env = &cpu->env;
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CPUX86State *env = &cpu->env;
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int ret = 0;
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int ret = 0;
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int n;
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int n;
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if (arch_info->exception == 1) {
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if (arch_info->exception == 1) {
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if (arch_info->dr6 & (1 << 14)) {
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if (arch_info->dr6 & (1 << 14)) {
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if (env->singlestep_enabled) {
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if (cs->singlestep_enabled) {
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ret = EXCP_DEBUG;
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ret = EXCP_DEBUG;
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}
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}
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} else {
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} else {
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@ -8255,6 +8255,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
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TranslationBlock *tb,
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TranslationBlock *tb,
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bool search_pc)
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bool search_pc)
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{
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{
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CPUState *cs = CPU(cpu);
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CPUX86State *env = &cpu->env;
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CPUX86State *env = &cpu->env;
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DisasContext dc1, *dc = &dc1;
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DisasContext dc1, *dc = &dc1;
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target_ulong pc_ptr;
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target_ulong pc_ptr;
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@ -8281,7 +8282,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
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dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
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dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
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dc->iopl = (flags >> IOPL_SHIFT) & 3;
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dc->iopl = (flags >> IOPL_SHIFT) & 3;
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dc->tf = (flags >> TF_SHIFT) & 1;
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dc->tf = (flags >> TF_SHIFT) & 1;
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dc->singlestep_enabled = env->singlestep_enabled;
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->cc_op = CC_OP_DYNAMIC;
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dc->cc_op = CC_OP_DYNAMIC;
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dc->cc_op_dirty = false;
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dc->cc_op_dirty = false;
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dc->cs_base = cs_base;
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dc->cs_base = cs_base;
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@ -8302,7 +8303,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
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dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
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dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
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#endif
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#endif
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dc->flags = flags;
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dc->flags = flags;
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dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
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dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
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(flags & HF_INHIBIT_IRQ_MASK)
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(flags & HF_INHIBIT_IRQ_MASK)
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#ifndef CONFIG_SOFTMMU
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#ifndef CONFIG_SOFTMMU
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|| (flags & HF_SOFTMMU_MASK)
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|| (flags & HF_SOFTMMU_MASK)
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@ -1015,6 +1015,7 @@ static inline
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void gen_intermediate_code_internal(LM32CPU *cpu,
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void gen_intermediate_code_internal(LM32CPU *cpu,
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TranslationBlock *tb, bool search_pc)
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TranslationBlock *tb, bool search_pc)
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{
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{
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CPUState *cs = CPU(cpu);
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CPULM32State *env = &cpu->env;
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CPULM32State *env = &cpu->env;
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struct DisasContext ctx, *dc = &ctx;
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struct DisasContext ctx, *dc = &ctx;
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uint16_t *gen_opc_end;
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uint16_t *gen_opc_end;
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@ -1032,7 +1033,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
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dc->is_jmp = DISAS_NEXT;
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dc->is_jmp = DISAS_NEXT;
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dc->pc = pc_start;
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dc->pc = pc_start;
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dc->singlestep_enabled = env->singlestep_enabled;
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->nr_nops = 0;
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dc->nr_nops = 0;
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if (pc_start & 3) {
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if (pc_start & 3) {
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@ -1077,7 +1078,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
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} while (!dc->is_jmp
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} while (!dc->is_jmp
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&& tcg_ctx.gen_opc_ptr < gen_opc_end
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&& tcg_ctx.gen_opc_ptr < gen_opc_end
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&& !env->singlestep_enabled
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&& !cs->singlestep_enabled
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&& !singlestep
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&& !singlestep
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&& (dc->pc < next_page_start)
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&& (dc->pc < next_page_start)
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&& num_insns < max_insns);
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&& num_insns < max_insns);
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@ -1086,7 +1087,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
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gen_io_end();
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gen_io_end();
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}
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}
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if (unlikely(env->singlestep_enabled)) {
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if (unlikely(cs->singlestep_enabled)) {
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if (dc->is_jmp == DISAS_NEXT) {
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if (dc->is_jmp == DISAS_NEXT) {
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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}
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}
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@ -2974,6 +2974,7 @@ static inline void
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gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
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gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
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bool search_pc)
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bool search_pc)
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{
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{
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CPUState *cs = CPU(cpu);
|
||||||
CPUM68KState *env = &cpu->env;
|
CPUM68KState *env = &cpu->env;
|
||||||
DisasContext dc1, *dc = &dc1;
|
DisasContext dc1, *dc = &dc1;
|
||||||
uint16_t *gen_opc_end;
|
uint16_t *gen_opc_end;
|
||||||
|
@ -2995,7 +2996,7 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
|
||||||
dc->is_jmp = DISAS_NEXT;
|
dc->is_jmp = DISAS_NEXT;
|
||||||
dc->pc = pc_start;
|
dc->pc = pc_start;
|
||||||
dc->cc_op = CC_OP_DYNAMIC;
|
dc->cc_op = CC_OP_DYNAMIC;
|
||||||
dc->singlestep_enabled = env->singlestep_enabled;
|
dc->singlestep_enabled = cs->singlestep_enabled;
|
||||||
dc->fpcr = env->fpcr;
|
dc->fpcr = env->fpcr;
|
||||||
dc->user = (env->sr & SR_S) == 0;
|
dc->user = (env->sr & SR_S) == 0;
|
||||||
dc->is_mem = 0;
|
dc->is_mem = 0;
|
||||||
|
@ -3038,14 +3039,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
|
||||||
disas_m68k_insn(env, dc);
|
disas_m68k_insn(env, dc);
|
||||||
num_insns++;
|
num_insns++;
|
||||||
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
|
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
|
||||||
!env->singlestep_enabled &&
|
!cs->singlestep_enabled &&
|
||||||
!singlestep &&
|
!singlestep &&
|
||||||
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
|
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
|
||||||
num_insns < max_insns);
|
num_insns < max_insns);
|
||||||
|
|
||||||
if (tb->cflags & CF_LAST_IO)
|
if (tb->cflags & CF_LAST_IO)
|
||||||
gen_io_end();
|
gen_io_end();
|
||||||
if (unlikely(env->singlestep_enabled)) {
|
if (unlikely(cs->singlestep_enabled)) {
|
||||||
/* Make sure the pc is updated, and raise a debug exception. */
|
/* Make sure the pc is updated, and raise a debug exception. */
|
||||||
if (!dc->is_jmp) {
|
if (!dc->is_jmp) {
|
||||||
gen_flush_cc_op(dc);
|
gen_flush_cc_op(dc);
|
||||||
|
|
|
@ -1741,6 +1741,7 @@ static inline void
|
||||||
gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
|
gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
|
||||||
bool search_pc)
|
bool search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
CPUMBState *env = &cpu->env;
|
CPUMBState *env = &cpu->env;
|
||||||
uint16_t *gen_opc_end;
|
uint16_t *gen_opc_end;
|
||||||
uint32_t pc_start;
|
uint32_t pc_start;
|
||||||
|
@ -1766,7 +1767,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
|
||||||
dc->jmp = JMP_INDIRECT;
|
dc->jmp = JMP_INDIRECT;
|
||||||
}
|
}
|
||||||
dc->pc = pc_start;
|
dc->pc = pc_start;
|
||||||
dc->singlestep_enabled = env->singlestep_enabled;
|
dc->singlestep_enabled = cs->singlestep_enabled;
|
||||||
dc->cpustate_changed = 0;
|
dc->cpustate_changed = 0;
|
||||||
dc->abort_at_next_insn = 0;
|
dc->abort_at_next_insn = 0;
|
||||||
dc->nr_nops = 0;
|
dc->nr_nops = 0;
|
||||||
|
@ -1859,8 +1860,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (env->singlestep_enabled)
|
if (cs->singlestep_enabled) {
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
} while (!dc->is_jmp && !dc->cpustate_changed
|
} while (!dc->is_jmp && !dc->cpustate_changed
|
||||||
&& tcg_ctx.gen_opc_ptr < gen_opc_end
|
&& tcg_ctx.gen_opc_ptr < gen_opc_end
|
||||||
&& !singlestep
|
&& !singlestep
|
||||||
|
@ -1887,7 +1889,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
|
||||||
}
|
}
|
||||||
t_sync_flags(dc);
|
t_sync_flags(dc);
|
||||||
|
|
||||||
if (unlikely(env->singlestep_enabled)) {
|
if (unlikely(cs->singlestep_enabled)) {
|
||||||
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
|
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
|
||||||
|
|
||||||
if (dc->is_jmp != DISAS_JUMP) {
|
if (dc->is_jmp != DISAS_JUMP) {
|
||||||
|
|
|
@ -15543,6 +15543,7 @@ static inline void
|
||||||
gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
||||||
bool search_pc)
|
bool search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
CPUMIPSState *env = &cpu->env;
|
CPUMIPSState *env = &cpu->env;
|
||||||
DisasContext ctx;
|
DisasContext ctx;
|
||||||
target_ulong pc_start;
|
target_ulong pc_start;
|
||||||
|
@ -15561,7 +15562,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
||||||
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
||||||
ctx.pc = pc_start;
|
ctx.pc = pc_start;
|
||||||
ctx.saved_pc = -1;
|
ctx.saved_pc = -1;
|
||||||
ctx.singlestep_enabled = env->singlestep_enabled;
|
ctx.singlestep_enabled = cs->singlestep_enabled;
|
||||||
ctx.insn_flags = env->insn_flags;
|
ctx.insn_flags = env->insn_flags;
|
||||||
ctx.tb = tb;
|
ctx.tb = tb;
|
||||||
ctx.bstate = BS_NONE;
|
ctx.bstate = BS_NONE;
|
||||||
|
@ -15637,8 +15638,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
||||||
This is what GDB expects and is consistent with what the
|
This is what GDB expects and is consistent with what the
|
||||||
hardware does (e.g. if a delay slot instruction faults, the
|
hardware does (e.g. if a delay slot instruction faults, the
|
||||||
reported PC is the PC of the branch). */
|
reported PC is the PC of the branch). */
|
||||||
if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
|
if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
|
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
|
||||||
break;
|
break;
|
||||||
|
@ -15653,9 +15655,10 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
||||||
if (singlestep)
|
if (singlestep)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (tb->cflags & CF_LAST_IO)
|
if (tb->cflags & CF_LAST_IO) {
|
||||||
gen_io_end();
|
gen_io_end();
|
||||||
if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) {
|
}
|
||||||
|
if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
|
||||||
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
|
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
|
||||||
gen_helper_0e0i(raise_exception, EXCP_DEBUG);
|
gen_helper_0e0i(raise_exception, EXCP_DEBUG);
|
||||||
} else {
|
} else {
|
||||||
|
|
|
@ -824,6 +824,7 @@ static inline void
|
||||||
gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
|
gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
|
||||||
bool search_pc)
|
bool search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
DisasContext ctx;
|
DisasContext ctx;
|
||||||
target_ulong pc_start;
|
target_ulong pc_start;
|
||||||
uint16_t *gen_opc_end;
|
uint16_t *gen_opc_end;
|
||||||
|
@ -871,7 +872,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
|
||||||
ctx.pc += decode_opc(cpu, &ctx);
|
ctx.pc += decode_opc(cpu, &ctx);
|
||||||
num_insns++;
|
num_insns++;
|
||||||
|
|
||||||
if (env->singlestep_enabled) {
|
if (cs->singlestep_enabled) {
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -880,7 +881,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
|
||||||
}
|
}
|
||||||
} while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end);
|
} while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end);
|
||||||
|
|
||||||
if (env->singlestep_enabled) {
|
if (cs->singlestep_enabled) {
|
||||||
tcg_gen_movi_tl(cpu_pc, ctx.pc);
|
tcg_gen_movi_tl(cpu_pc, ctx.pc);
|
||||||
gen_helper_debug(cpu_env);
|
gen_helper_debug(cpu_env);
|
||||||
} else {
|
} else {
|
||||||
|
|
|
@ -1662,6 +1662,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
|
||||||
TranslationBlock *tb,
|
TranslationBlock *tb,
|
||||||
int search_pc)
|
int search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
struct DisasContext ctx, *dc = &ctx;
|
struct DisasContext ctx, *dc = &ctx;
|
||||||
uint16_t *gen_opc_end;
|
uint16_t *gen_opc_end;
|
||||||
uint32_t pc_start;
|
uint32_t pc_start;
|
||||||
|
@ -1681,7 +1682,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
|
||||||
dc->mem_idx = cpu_mmu_index(&cpu->env);
|
dc->mem_idx = cpu_mmu_index(&cpu->env);
|
||||||
dc->synced_flags = dc->tb_flags = tb->flags;
|
dc->synced_flags = dc->tb_flags = tb->flags;
|
||||||
dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
|
dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
|
||||||
dc->singlestep_enabled = cpu->env.singlestep_enabled;
|
dc->singlestep_enabled = cs->singlestep_enabled;
|
||||||
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
||||||
qemu_log("-----------------------------------------\n");
|
qemu_log("-----------------------------------------\n");
|
||||||
log_cpu_state(CPU(cpu), 0);
|
log_cpu_state(CPU(cpu), 0);
|
||||||
|
@ -1743,7 +1744,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
|
||||||
}
|
}
|
||||||
} while (!dc->is_jmp
|
} while (!dc->is_jmp
|
||||||
&& tcg_ctx.gen_opc_ptr < gen_opc_end
|
&& tcg_ctx.gen_opc_ptr < gen_opc_end
|
||||||
&& !cpu->env.singlestep_enabled
|
&& !cs->singlestep_enabled
|
||||||
&& !singlestep
|
&& !singlestep
|
||||||
&& (dc->pc < next_page_start)
|
&& (dc->pc < next_page_start)
|
||||||
&& num_insns < max_insns);
|
&& num_insns < max_insns);
|
||||||
|
@ -1755,7 +1756,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
|
||||||
dc->is_jmp = DISAS_UPDATE;
|
dc->is_jmp = DISAS_UPDATE;
|
||||||
tcg_gen_movi_tl(cpu_pc, dc->pc);
|
tcg_gen_movi_tl(cpu_pc, dc->pc);
|
||||||
}
|
}
|
||||||
if (unlikely(cpu->env.singlestep_enabled)) {
|
if (unlikely(cs->singlestep_enabled)) {
|
||||||
if (dc->is_jmp == DISAS_NEXT) {
|
if (dc->is_jmp == DISAS_NEXT) {
|
||||||
tcg_gen_movi_tl(cpu_pc, dc->pc);
|
tcg_gen_movi_tl(cpu_pc, dc->pc);
|
||||||
}
|
}
|
||||||
|
|
|
@ -9730,6 +9730,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
|
||||||
TranslationBlock *tb,
|
TranslationBlock *tb,
|
||||||
bool search_pc)
|
bool search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
CPUPPCState *env = &cpu->env;
|
CPUPPCState *env = &cpu->env;
|
||||||
DisasContext ctx, *ctxp = &ctx;
|
DisasContext ctx, *ctxp = &ctx;
|
||||||
opc_handler_t **table, *handler;
|
opc_handler_t **table, *handler;
|
||||||
|
@ -9770,8 +9771,9 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
|
||||||
ctx.singlestep_enabled = 0;
|
ctx.singlestep_enabled = 0;
|
||||||
if ((env->flags & POWERPC_FLAG_BE) && msr_be)
|
if ((env->flags & POWERPC_FLAG_BE) && msr_be)
|
||||||
ctx.singlestep_enabled |= CPU_BRANCH_STEP;
|
ctx.singlestep_enabled |= CPU_BRANCH_STEP;
|
||||||
if (unlikely(env->singlestep_enabled))
|
if (unlikely(cs->singlestep_enabled)) {
|
||||||
ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
|
ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
|
||||||
|
}
|
||||||
#if defined (DO_SINGLE_STEP) && 0
|
#if defined (DO_SINGLE_STEP) && 0
|
||||||
/* Single step trace mode */
|
/* Single step trace mode */
|
||||||
msr_se = 1;
|
msr_se = 1;
|
||||||
|
@ -9873,7 +9875,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
|
||||||
ctx.exception != POWERPC_EXCP_BRANCH)) {
|
ctx.exception != POWERPC_EXCP_BRANCH)) {
|
||||||
gen_exception(ctxp, POWERPC_EXCP_TRACE);
|
gen_exception(ctxp, POWERPC_EXCP_TRACE);
|
||||||
} else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
|
} else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
|
||||||
(env->singlestep_enabled) ||
|
(cs->singlestep_enabled) ||
|
||||||
singlestep ||
|
singlestep ||
|
||||||
num_insns >= max_insns)) {
|
num_insns >= max_insns)) {
|
||||||
/* if we reach a page boundary or are single stepping, stop
|
/* if we reach a page boundary or are single stepping, stop
|
||||||
|
@ -9887,7 +9889,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
|
||||||
if (ctx.exception == POWERPC_EXCP_NONE) {
|
if (ctx.exception == POWERPC_EXCP_NONE) {
|
||||||
gen_goto_tb(&ctx, 0, ctx.nip);
|
gen_goto_tb(&ctx, 0, ctx.nip);
|
||||||
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
|
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
|
||||||
if (unlikely(env->singlestep_enabled)) {
|
if (unlikely(cs->singlestep_enabled)) {
|
||||||
gen_debug_exception(ctxp);
|
gen_debug_exception(ctxp);
|
||||||
}
|
}
|
||||||
/* Generate the return instruction */
|
/* Generate the return instruction */
|
||||||
|
|
|
@ -4740,6 +4740,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
|
||||||
TranslationBlock *tb,
|
TranslationBlock *tb,
|
||||||
bool search_pc)
|
bool search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
CPUS390XState *env = &cpu->env;
|
CPUS390XState *env = &cpu->env;
|
||||||
DisasContext dc;
|
DisasContext dc;
|
||||||
target_ulong pc_start;
|
target_ulong pc_start;
|
||||||
|
@ -4761,7 +4762,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
|
||||||
dc.tb = tb;
|
dc.tb = tb;
|
||||||
dc.pc = pc_start;
|
dc.pc = pc_start;
|
||||||
dc.cc_op = CC_OP_DYNAMIC;
|
dc.cc_op = CC_OP_DYNAMIC;
|
||||||
do_debug = dc.singlestep_enabled = env->singlestep_enabled;
|
do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
|
||||||
|
|
||||||
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
||||||
|
|
||||||
|
@ -4818,7 +4819,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
|
||||||
|| tcg_ctx.gen_opc_ptr >= gen_opc_end
|
|| tcg_ctx.gen_opc_ptr >= gen_opc_end
|
||||||
|| num_insns >= max_insns
|
|| num_insns >= max_insns
|
||||||
|| singlestep
|
|| singlestep
|
||||||
|| env->singlestep_enabled)) {
|
|| cs->singlestep_enabled)) {
|
||||||
status = EXIT_PC_STALE;
|
status = EXIT_PC_STALE;
|
||||||
}
|
}
|
||||||
} while (status == NO_EXIT);
|
} while (status == NO_EXIT);
|
||||||
|
|
|
@ -1849,6 +1849,7 @@ static inline void
|
||||||
gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
|
gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
|
||||||
bool search_pc)
|
bool search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
CPUSH4State *env = &cpu->env;
|
CPUSH4State *env = &cpu->env;
|
||||||
DisasContext ctx;
|
DisasContext ctx;
|
||||||
target_ulong pc_start;
|
target_ulong pc_start;
|
||||||
|
@ -1868,7 +1869,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
|
||||||
so assume it is a dynamic branch. */
|
so assume it is a dynamic branch. */
|
||||||
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
|
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
|
||||||
ctx.tb = tb;
|
ctx.tb = tb;
|
||||||
ctx.singlestep_enabled = env->singlestep_enabled;
|
ctx.singlestep_enabled = cs->singlestep_enabled;
|
||||||
ctx.features = env->features;
|
ctx.features = env->features;
|
||||||
ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
|
ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
|
||||||
|
|
||||||
|
@ -1914,8 +1915,9 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
|
||||||
ctx.pc += 2;
|
ctx.pc += 2;
|
||||||
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
|
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
|
||||||
break;
|
break;
|
||||||
if (env->singlestep_enabled)
|
if (cs->singlestep_enabled) {
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
if (num_insns >= max_insns)
|
if (num_insns >= max_insns)
|
||||||
break;
|
break;
|
||||||
if (singlestep)
|
if (singlestep)
|
||||||
|
@ -1923,7 +1925,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
|
||||||
}
|
}
|
||||||
if (tb->cflags & CF_LAST_IO)
|
if (tb->cflags & CF_LAST_IO)
|
||||||
gen_io_end();
|
gen_io_end();
|
||||||
if (env->singlestep_enabled) {
|
if (cs->singlestep_enabled) {
|
||||||
tcg_gen_movi_i32(cpu_pc, ctx.pc);
|
tcg_gen_movi_i32(cpu_pc, ctx.pc);
|
||||||
gen_helper_debug(cpu_env);
|
gen_helper_debug(cpu_env);
|
||||||
} else {
|
} else {
|
||||||
|
|
|
@ -5223,6 +5223,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
|
||||||
TranslationBlock *tb,
|
TranslationBlock *tb,
|
||||||
bool spc)
|
bool spc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
CPUSPARCState *env = &cpu->env;
|
CPUSPARCState *env = &cpu->env;
|
||||||
target_ulong pc_start, last_pc;
|
target_ulong pc_start, last_pc;
|
||||||
uint16_t *gen_opc_end;
|
uint16_t *gen_opc_end;
|
||||||
|
@ -5244,7 +5245,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
|
||||||
dc->def = env->def;
|
dc->def = env->def;
|
||||||
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
|
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
|
||||||
dc->address_mask_32bit = tb_am_enabled(tb->flags);
|
dc->address_mask_32bit = tb_am_enabled(tb->flags);
|
||||||
dc->singlestep = (env->singlestep_enabled || singlestep);
|
dc->singlestep = (cs->singlestep_enabled || singlestep);
|
||||||
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
||||||
|
|
||||||
num_insns = 0;
|
num_insns = 0;
|
||||||
|
|
|
@ -1879,6 +1879,7 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
|
||||||
static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
|
static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
|
||||||
TranslationBlock *tb, bool search_pc)
|
TranslationBlock *tb, bool search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
CPUUniCore32State *env = &cpu->env;
|
CPUUniCore32State *env = &cpu->env;
|
||||||
DisasContext dc1, *dc = &dc1;
|
DisasContext dc1, *dc = &dc1;
|
||||||
CPUBreakpoint *bp;
|
CPUBreakpoint *bp;
|
||||||
|
@ -1900,7 +1901,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
|
||||||
|
|
||||||
dc->is_jmp = DISAS_NEXT;
|
dc->is_jmp = DISAS_NEXT;
|
||||||
dc->pc = pc_start;
|
dc->pc = pc_start;
|
||||||
dc->singlestep_enabled = env->singlestep_enabled;
|
dc->singlestep_enabled = cs->singlestep_enabled;
|
||||||
dc->condjmp = 0;
|
dc->condjmp = 0;
|
||||||
cpu_F0s = tcg_temp_new_i32();
|
cpu_F0s = tcg_temp_new_i32();
|
||||||
cpu_F1s = tcg_temp_new_i32();
|
cpu_F1s = tcg_temp_new_i32();
|
||||||
|
@ -1971,7 +1972,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
|
||||||
* ensures prefetch aborts occur at the right place. */
|
* ensures prefetch aborts occur at the right place. */
|
||||||
num_insns++;
|
num_insns++;
|
||||||
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
|
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
|
||||||
!env->singlestep_enabled &&
|
!cs->singlestep_enabled &&
|
||||||
!singlestep &&
|
!singlestep &&
|
||||||
dc->pc < next_page_start &&
|
dc->pc < next_page_start &&
|
||||||
num_insns < max_insns);
|
num_insns < max_insns);
|
||||||
|
@ -1988,7 +1989,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
|
||||||
/* At this stage dc->condjmp will only be set when the skipped
|
/* At this stage dc->condjmp will only be set when the skipped
|
||||||
instruction was a conditional branch or trap, and the PC has
|
instruction was a conditional branch or trap, and the PC has
|
||||||
already been written. */
|
already been written. */
|
||||||
if (unlikely(env->singlestep_enabled)) {
|
if (unlikely(cs->singlestep_enabled)) {
|
||||||
/* Make sure the pc is updated, and raise a debug exception. */
|
/* Make sure the pc is updated, and raise a debug exception. */
|
||||||
if (dc->condjmp) {
|
if (dc->condjmp) {
|
||||||
if (dc->is_jmp == DISAS_SYSCALL) {
|
if (dc->is_jmp == DISAS_SYSCALL) {
|
||||||
|
|
|
@ -2879,6 +2879,7 @@ static inline
|
||||||
void gen_intermediate_code_internal(XtensaCPU *cpu,
|
void gen_intermediate_code_internal(XtensaCPU *cpu,
|
||||||
TranslationBlock *tb, bool search_pc)
|
TranslationBlock *tb, bool search_pc)
|
||||||
{
|
{
|
||||||
|
CPUState *cs = CPU(cpu);
|
||||||
CPUXtensaState *env = &cpu->env;
|
CPUXtensaState *env = &cpu->env;
|
||||||
DisasContext dc;
|
DisasContext dc;
|
||||||
int insn_count = 0;
|
int insn_count = 0;
|
||||||
|
@ -2894,7 +2895,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
|
||||||
}
|
}
|
||||||
|
|
||||||
dc.config = env->config;
|
dc.config = env->config;
|
||||||
dc.singlestep_enabled = env->singlestep_enabled;
|
dc.singlestep_enabled = cs->singlestep_enabled;
|
||||||
dc.tb = tb;
|
dc.tb = tb;
|
||||||
dc.pc = pc_start;
|
dc.pc = pc_start;
|
||||||
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
|
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
|
||||||
|
@ -2917,7 +2918,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
|
||||||
|
|
||||||
gen_tb_start();
|
gen_tb_start();
|
||||||
|
|
||||||
if (env->singlestep_enabled && env->exception_taken) {
|
if (cs->singlestep_enabled && env->exception_taken) {
|
||||||
env->exception_taken = 0;
|
env->exception_taken = 0;
|
||||||
tcg_gen_movi_i32(cpu_pc, dc.pc);
|
tcg_gen_movi_i32(cpu_pc, dc.pc);
|
||||||
gen_exception(&dc, EXCP_DEBUG);
|
gen_exception(&dc, EXCP_DEBUG);
|
||||||
|
@ -2970,7 +2971,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
|
||||||
if (dc.icount) {
|
if (dc.icount) {
|
||||||
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
|
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
|
||||||
}
|
}
|
||||||
if (env->singlestep_enabled) {
|
if (cs->singlestep_enabled) {
|
||||||
tcg_gen_movi_i32(cpu_pc, dc.pc);
|
tcg_gen_movi_i32(cpu_pc, dc.pc);
|
||||||
gen_exception(&dc, EXCP_DEBUG);
|
gen_exception(&dc, EXCP_DEBUG);
|
||||||
break;
|
break;
|
||||||
|
|
Loading…
Reference in New Issue