hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC
Implement support for using the KVM in-kernel GIC for ARM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
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Peter Maydell
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eb035b48d5
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ed46676160
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@ -19,6 +19,7 @@
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*/
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#include "sysbus.h"
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#include "sysemu/kvm.h"
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/* A15MP private memory region. */
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@ -40,8 +41,13 @@ static int a15mp_priv_init(SysBusDevice *dev)
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{
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A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev);
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SysBusDevice *busdev;
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const char *gictype = "arm_gic";
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s->gic = qdev_create(NULL, "arm_gic");
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if (kvm_irqchip_in_kernel()) {
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gictype = "kvm-arm-gic";
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}
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s->gic = qdev_create(NULL, gictype);
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qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
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qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
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qdev_prop_set_uint32(s->gic, "revision", 2);
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@ -32,5 +32,6 @@ obj-y += collie.o
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obj-y += imx_serial.o imx_ccm.o imx_timer.o imx_avic.o
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obj-y += kzm.o
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obj-$(CONFIG_FDT) += ../device_tree.o
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obj-$(CONFIG_KVM) += kvm/arm_gic.o
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obj-y := $(addprefix ../,$(obj-y))
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@ -0,0 +1,167 @@
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/*
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* ARM Generic Interrupt Controller using KVM in-kernel support
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/sysbus.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "hw/arm_gic_internal.h"
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#define TYPE_KVM_ARM_GIC "kvm-arm-gic"
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#define KVM_ARM_GIC(obj) \
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OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
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#define KVM_ARM_GIC_CLASS(klass) \
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OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
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#define KVM_ARM_GIC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
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typedef struct KVMARMGICClass {
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ARMGICCommonClass parent_class;
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DeviceRealize parent_realize;
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void (*parent_reset)(DeviceState *dev);
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} KVMARMGICClass;
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static void kvm_arm_gic_set_irq(void *opaque, int irq, int level)
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{
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/* Meaning of the 'irq' parameter:
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* [0..N-1] : external interrupts
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* [N..N+31] : PPI (internal) interrupts for CPU 0
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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* Convert this to the kernel's desired encoding, which
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* has separate fields in the irq number for type,
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* CPU number and interrupt number.
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*/
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GICState *s = (GICState *)opaque;
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int kvm_irq, irqtype, cpu;
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if (irq < (s->num_irq - GIC_INTERNAL)) {
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/* External interrupt. The kernel numbers these like the GIC
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* hardware, with external interrupt IDs starting after the
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* internal ones.
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*/
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irqtype = KVM_ARM_IRQ_TYPE_SPI;
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cpu = 0;
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irq += GIC_INTERNAL;
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} else {
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/* Internal interrupt: decode into (cpu, interrupt id) */
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irqtype = KVM_ARM_IRQ_TYPE_PPI;
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irq -= (s->num_irq - GIC_INTERNAL);
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cpu = irq / GIC_INTERNAL;
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irq %= GIC_INTERNAL;
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}
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kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
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| (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
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kvm_set_irq(kvm_state, kvm_irq, !!level);
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}
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static void kvm_arm_gic_put(GICState *s)
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{
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/* TODO: there isn't currently a kernel interface to set the GIC state */
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}
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static void kvm_arm_gic_get(GICState *s)
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{
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/* TODO: there isn't currently a kernel interface to get the GIC state */
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}
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static void kvm_arm_gic_reset(DeviceState *dev)
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{
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GICState *s = ARM_GIC_COMMON(dev);
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KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
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kgc->parent_reset(dev);
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kvm_arm_gic_put(s);
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}
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static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
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{
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int i;
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GICState *s = KVM_ARM_GIC(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
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kgc->parent_realize(dev, errp);
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if (error_is_set(errp)) {
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return;
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}
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i = s->num_irq - GIC_INTERNAL;
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/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
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* GPIO array layout is thus:
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* [0..N-1] SPIs
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* [N..N+31] PPIs for CPU 0
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* [N+32..N+63] PPIs for CPU 1
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* ...
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*/
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i += (GIC_INTERNAL * s->num_cpu);
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qdev_init_gpio_in(dev, kvm_arm_gic_set_irq, i);
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/* We never use our outbound IRQ lines but provide them so that
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* we maintain the same interface as the non-KVM GIC.
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*/
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->parent_irq[i]);
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}
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/* Distributor */
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memory_region_init_reservation(&s->iomem, "kvm-gic_dist", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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kvm_arm_register_device(&s->iomem,
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(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
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| KVM_VGIC_V2_ADDR_TYPE_DIST);
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/* CPU interface for current core. Unlike arm_gic, we don't
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* provide the "interface for core #N" memory regions, because
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* cores with a VGIC don't have those.
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*/
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memory_region_init_reservation(&s->cpuiomem[0], "kvm-gic_cpu", 0x1000);
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sysbus_init_mmio(sbd, &s->cpuiomem[0]);
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kvm_arm_register_device(&s->cpuiomem[0],
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(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
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| KVM_VGIC_V2_ADDR_TYPE_CPU);
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}
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static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
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KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
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agcc->pre_save = kvm_arm_gic_get;
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agcc->post_load = kvm_arm_gic_put;
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kgc->parent_realize = dc->realize;
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kgc->parent_reset = dc->reset;
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dc->realize = kvm_arm_gic_realize;
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dc->reset = kvm_arm_gic_reset;
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dc->no_user = 1;
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}
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static const TypeInfo kvm_arm_gic_info = {
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.name = TYPE_KVM_ARM_GIC,
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.parent = TYPE_ARM_GIC_COMMON,
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.instance_size = sizeof(GICState),
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.class_init = kvm_arm_gic_class_init,
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.class_size = sizeof(KVMARMGICClass),
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};
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static void kvm_arm_gic_register_types(void)
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{
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type_register_static(&kvm_arm_gic_info);
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}
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type_init(kvm_arm_gic_register_types)
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