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target/arm: Convert Move wide (immediate) to decodetree

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Convert the MON, MOVZ, MOVK instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-11-peter.maydell@linaro.org
[PMM: Rebased]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-12 15:40:56 +01:00 committed by Peter Maydell
parent 8127f46a5b
commit ee0daeb946
2 changed files with 42 additions and 44 deletions
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13
target/arm/tcg/a64.decode
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@ -71,3 +71,16 @@ EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64
EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32
ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64
ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32
# Move wide (immediate)
&movw rd sf imm hw
@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1
@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0
MOVN . 00 100101 .. ................ ..... @movw_64
MOVN . 00 100101 .. ................ ..... @movw_32
MOVZ . 10 100101 .. ................ ..... @movw_64
MOVZ . 10 100101 .. ................ ..... @movw_32
MOVK . 11 100101 .. ................ ..... @movw_64
MOVK . 11 100101 .. ................ ..... @movw_32

73
target/arm/tcg/translate-a64.c
View File

@ -4395,52 +4395,40 @@ TRANS(ANDS_i, gen_rri_log, a, true, tcg_gen_andi_i64)
/* /*
* Move wide (immediate) * Move wide (immediate)
*
* 31 30 29 28 23 22 21 20 5 4 0
* +--+-----+-------------+-----+----------------+------+
* |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
* +--+-----+-------------+-----+----------------+------+
*
* sf: 0 -> 32 bit, 1 -> 64 bit
* opc: 00 -> N, 10 -> Z, 11 -> K
* hw: shift/16 (0,16, and sf only 32, 48)
*/ */
static void disas_movw_imm(DisasContext *s, uint32_t insn)
static bool trans_MOVZ(DisasContext *s, arg_movw *a)
{ {
int rd = extract32(insn, 0, 5); int pos = a->hw << 4;
uint64_t imm = extract32(insn, 5, 16); tcg_gen_movi_i64(cpu_reg(s, a->rd), (uint64_t)a->imm << pos);
int sf = extract32(insn, 31, 1); return true;
int opc = extract32(insn, 29, 2); }
int pos = extract32(insn, 21, 2) << 4;
TCGv_i64 tcg_rd = cpu_reg(s, rd);
if (!sf && (pos >= 32)) { static bool trans_MOVN(DisasContext *s, arg_movw *a)
unallocated_encoding(s); {
return; int pos = a->hw << 4;
} uint64_t imm = a->imm;
switch (opc) { imm = ~(imm << pos);
case 0: /* MOVN */ if (!a->sf) {
case 2: /* MOVZ */ imm = (uint32_t)imm;
imm <<= pos;
if (opc == 0) {
imm = ~imm;
}
if (!sf) {
imm &= 0xffffffffu;
}
tcg_gen_movi_i64(tcg_rd, imm);
break;
case 3: /* MOVK */
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16);
if (!sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
break;
default:
unallocated_encoding(s);
break;
} }
tcg_gen_movi_i64(cpu_reg(s, a->rd), imm);
return true;
}
static bool trans_MOVK(DisasContext *s, arg_movw *a)
{
int pos = a->hw << 4;
TCGv_i64 tcg_rd, tcg_im;
tcg_rd = cpu_reg(s, a->rd);
tcg_im = tcg_constant_i64(a->imm);
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_im, pos, 16);
if (!a->sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
return true;
} }
/* Bitfield /* Bitfield
@ -4585,9 +4573,6 @@ static void disas_extract(DisasContext *s, uint32_t insn)
static void disas_data_proc_imm(DisasContext *s, uint32_t insn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
{ {
switch (extract32(insn, 23, 6)) { switch (extract32(insn, 23, 6)) {
case 0x25: /* Move wide (immediate) */
disas_movw_imm(s, insn);
break;
case 0x26: /* Bitfield */ case 0x26: /* Bitfield */
disas_bitfield(s, insn); disas_bitfield(s, insn);
break; break;