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target/riscv: rvv-1.0: iota instruction 

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-33-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:18 +08:00 committed by Alistair Francis
parent 40c1495d69
commit ee17eaa120
2 changed files with 9 additions and 3 deletions
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2
target/riscv/insn32.decode
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@ -632,7 +632,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2

10
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -2757,12 +2757,18 @@ GEN_M_TRANS(vmsbf_m)
GEN_M_TRANS(vmsif_m)
GEN_M_TRANS(vmsof_m)
/* Vector Iota Instruction */
/*
* Vector Iota Instruction
*
* 1. The destination register cannot overlap the source register.
* 2. If masked, cannot overlap the mask register ('v0').
* 3. An illegal instruction exception is raised if vstart is non-zero.
*/
static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s) &&
require_noover(a->rd, s->lmul, a->rs2, 0) &&
!is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
require_vm(a->vm, a->rd) &&
require_align(a->rd, s->lmul)) {
uint32_t data = 0;