target/loongarch: Add branch instruction translation
This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-16-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Song Gao
Richard Henderson
parent
e616bdfd01
commit
ee86bd58b8
83
target/loongarch/insn_trans/trans_branch.c.inc
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83
target/loongarch/insn_trans/trans_branch.c.inc
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@ -0,0 +1,83 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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static bool trans_b(DisasContext *ctx, arg_b *a)
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{
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gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool trans_bl(DisasContext *ctx, arg_bl *a)
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{
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tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
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gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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tcg_gen_addi_tl(cpu_pc, src1, a->offs);
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tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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tcg_gen_lookup_and_goto_ptr();
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static void gen_bc(DisasContext *ctx, TCGv src1, TCGv src2,
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target_long offs, TCGCond cond)
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{
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TCGLabel *l = gen_new_label();
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tcg_gen_brcond_tl(cond, src1, src2, l);
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gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
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gen_set_label(l);
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gen_goto_tb(ctx, 0, ctx->base.pc_next + offs);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static bool gen_rr_bc(DisasContext *ctx, arg_rr_offs *a, TCGCond cond)
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{
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
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gen_bc(ctx, src1, src2, a->offs, cond);
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return true;
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}
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static bool gen_rz_bc(DisasContext *ctx, arg_r_offs *a, TCGCond cond)
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{
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = tcg_constant_tl(0);
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gen_bc(ctx, src1, src2, a->offs, cond);
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return true;
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}
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static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, TCGCond cond)
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{
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TCGv src1 = tcg_temp_new();
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TCGv src2 = tcg_constant_tl(0);
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tcg_gen_ld8u_tl(src1, cpu_env,
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offsetof(CPULoongArchState, cf[a->cj]));
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gen_bc(ctx, src1, src2, a->offs, cond);
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return true;
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}
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TRANS(beq, gen_rr_bc, TCG_COND_EQ)
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TRANS(bne, gen_rr_bc, TCG_COND_NE)
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TRANS(blt, gen_rr_bc, TCG_COND_LT)
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TRANS(bge, gen_rr_bc, TCG_COND_GE)
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TRANS(bltu, gen_rr_bc, TCG_COND_LTU)
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TRANS(bgeu, gen_rr_bc, TCG_COND_GEU)
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TRANS(beqz, gen_rz_bc, TCG_COND_EQ)
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TRANS(bnez, gen_rz_bc, TCG_COND_NE)
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TRANS(bceqz, gen_cz_bc, TCG_COND_EQ)
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TRANS(bcnez, gen_cz_bc, TCG_COND_NE)
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@ -10,6 +10,9 @@
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#
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%i14s2 10:s14 !function=shl_2
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%sa2p1 15:2 !function=plus_1
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%offs21 0:s5 10:16 !function=shl_2
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%offs16 10:s16 !function=shl_2
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%offs26 0:s10 10:16 !function=shl_2
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#
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# Argument sets
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@ -38,6 +41,10 @@
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&rc rd cj
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&frr fd rj rk
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&fr_i fd rj imm
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&r_offs rj offs
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&c_offs cj offs
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&offs offs
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&rr_offs rj rd offs
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#
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# Formats
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@ -74,6 +81,10 @@
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@rc .... ........ ..... ..... .. cj:3 rd:5 &rc
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@frr .... ........ ..... rk:5 rj:5 fd:5 &frr
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@fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i
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@r_offs21 .... .. ................ rj:5 ..... &r_offs offs=%offs21
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@c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21
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@offs26 .... .. .......................... &offs offs=%offs26
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@rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
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#
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# Fixed point arithmetic operation instruction
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@ -409,3 +420,20 @@ fstgt_s 0011 10000111 01100 ..... ..... ..... @frr
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fstgt_d 0011 10000111 01101 ..... ..... ..... @frr
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fstle_s 0011 10000111 01110 ..... ..... ..... @frr
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fstle_d 0011 10000111 01111 ..... ..... ..... @frr
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#
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# Branch instructions
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#
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beqz 0100 00 ................ ..... ..... @r_offs21
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bnez 0100 01 ................ ..... ..... @r_offs21
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bceqz 0100 10 ................ 00 ... ..... @c_offs21
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bcnez 0100 10 ................ 01 ... ..... @c_offs21
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jirl 0100 11 ................ ..... ..... @rr_offs16
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b 0101 00 .......................... @offs26
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bl 0101 01 .......................... @offs26
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beq 0101 10 ................ ..... ..... @rr_offs16
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bne 0101 11 ................ ..... ..... @rr_offs16
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blt 0110 00 ................ ..... ..... @rr_offs16
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bge 0110 01 ................ ..... ..... @rr_offs16
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bltu 0110 10 ................ ..... ..... @rr_offs16
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bgeu 0110 11 ................ ..... ..... @rr_offs16
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@ -171,6 +171,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
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#include "insn_trans/trans_fcnv.c.inc"
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#include "insn_trans/trans_fmov.c.inc"
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#include "insn_trans/trans_fmemory.c.inc"
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#include "insn_trans/trans_branch.c.inc"
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static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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