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hw/mips/malta: Set CPU frequency to 320 MHz

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The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create
a 'cpuclk' output clock and connect it to the CPU input clock.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-20-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-10-12 11:58:02 +02:00
parent 6b290b41cb
commit eea1f5bac6
1 changed files with 16 additions and 3 deletions
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19
hw/mips/malta.c
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@ -26,6 +26,7 @@
#include "qemu/units.h" #include "qemu/units.h"
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
#include "hw/clock.h"
#include "hw/southbridge/piix.h" #include "hw/southbridge/piix.h"
#include "hw/isa/superio.h" #include "hw/isa/superio.h"
#include "hw/char/serial.h" #include "hw/char/serial.h"
@ -57,6 +58,7 @@
#include "sysemu/kvm.h" #include "sysemu/kvm.h"
#include "hw/semihosting/semihost.h" #include "hw/semihosting/semihost.h"
#include "hw/mips/cps.h" #include "hw/mips/cps.h"
#include "hw/qdev-clock.h"
#define ENVP_ADDR 0x80002000l #define ENVP_ADDR 0x80002000l
#define ENVP_NB_ENTRIES 16 #define ENVP_NB_ENTRIES 16
@ -94,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
struct MaltaState { struct MaltaState {
SysBusDevice parent_obj; SysBusDevice parent_obj;
Clock *cpuclk;
MIPSCPSState cps; MIPSCPSState cps;
qemu_irq i8259[ISA_NUM_IRQS]; qemu_irq i8259[ISA_NUM_IRQS];
}; };
@ -1159,7 +1162,7 @@ static void main_cpu_reset(void *opaque)
} }
} }
static void create_cpu_without_cps(MachineState *ms, static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
qemu_irq *cbus_irq, qemu_irq *i8259_irq) qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{ {
CPUMIPSState *env; CPUMIPSState *env;
@ -1167,7 +1170,7 @@ static void create_cpu_without_cps(MachineState *ms,
int i; int i;
for (i = 0; i < ms->smp.cpus; i++) { for (i = 0; i < ms->smp.cpus; i++) {
cpu = MIPS_CPU(cpu_create(ms->cpu_type)); cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
/* Init internal devices */ /* Init internal devices */
cpu_mips_irq_init_cpu(cpu); cpu_mips_irq_init_cpu(cpu);
@ -1189,6 +1192,7 @@ static void create_cps(MachineState *ms, MaltaState *s,
&error_fatal); &error_fatal);
object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
&error_fatal); &error_fatal);
qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
@ -1203,7 +1207,7 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) {
create_cps(ms, s, cbus_irq, i8259_irq); create_cps(ms, s, cbus_irq, i8259_irq);
} else { } else {
create_cpu_without_cps(ms, cbus_irq, i8259_irq); create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
} }
} }
@ -1421,10 +1425,19 @@ void mips_malta_init(MachineState *machine)
pci_vga_init(pci_bus); pci_vga_init(pci_bus);
} }
static void mips_malta_instance_init(Object *obj)
{
MaltaState *s = MIPS_MALTA(obj);
s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */
}
static const TypeInfo mips_malta_device = { static const TypeInfo mips_malta_device = {
.name = TYPE_MIPS_MALTA, .name = TYPE_MIPS_MALTA,
.parent = TYPE_SYS_BUS_DEVICE, .parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MaltaState), .instance_size = sizeof(MaltaState),
.instance_init = mips_malta_instance_init,
}; };
static void mips_malta_machine_init(MachineClass *mc) static void mips_malta_machine_init(MachineClass *mc)