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Stellaris ethernet support.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3728 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2007-11-24 03:13:04 +00:00
parent e57ec0168c
commit eea589cc22
5 changed files with 371 additions and 4 deletions
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2
Makefile.target
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@ -490,7 +490,7 @@ VL_OBJS+= integratorcp.o versatilepb.o ps2.o smc91c111.o arm_pic.o arm_timer.o
VL_OBJS+= arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
VL_OBJS+= versatile_pci.o sd.o ptimer.o
VL_OBJS+= realview_gic.o realview.o arm_sysctl.o mpcore.o
VL_OBJS+= armv7m.o armv7m_nvic.o stellaris.o pl022.o
VL_OBJS+= armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
VL_OBJS+= pl061.o
VL_OBJS+= arm-semi.o
VL_OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o

3
hw/arm-misc.h
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@ -30,5 +30,8 @@ void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
int system_clock_scale;
qemu_irq *armv7m_nvic_init(CPUState *env);
/* stellaris_enent.c */
void stellaris_enet_init(NICInfo *nd, uint32_t base, qemu_irq irq);
#endif /* !ARM_MISC_H */

4
hw/armv7m_nvic.c
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@ -14,7 +14,9 @@
#include "qemu-timer.h"
#include "arm-misc.h"
#define GIC_NIRQ 64
/* 32 internal lines (16 used for system exceptions) plus 64 external
interrupt lines. */
#define GIC_NIRQ 96
#define NCPU 1
#define NVIC 1

19
hw/stellaris.c
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@ -13,6 +13,7 @@
#include "devices.h"
#include "qemu-timer.h"
#include "i2c.h"
#include "net.h"
#include "sysemu.h"
#include "boards.h"
@ -319,6 +320,8 @@ typedef struct {
uint32_t dcgc[3];
uint32_t clkvclr;
uint32_t ldoarst;
uint32_t user0;
uint32_t user1;
qemu_irq irq;
stellaris_board_info *board;
} ssys_state;
@ -438,6 +441,10 @@ static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
return s->clkvclr;
case 0x160: /* LDOARST */
return s->ldoarst;
case 0x1e0: /* USER0 */
return s->user0;
case 0x1e4: /* USER1 */
return s->user1;
default:
cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n", (int)offset);
return 0;
@ -541,7 +548,8 @@ static void ssys_reset(void *opaque)
}
static void stellaris_sys_init(uint32_t base, qemu_irq irq,
stellaris_board_info * board)
stellaris_board_info * board,
uint8_t *macaddr)
{
int iomemtype;
ssys_state *s;
@ -550,6 +558,9 @@ static void stellaris_sys_init(uint32_t base, qemu_irq irq,
s->base = base;
s->irq = irq;
s->board = board;
/* Most devices come preprogrammed with a MAC address in the user data. */
s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
iomemtype = cpu_register_io_memory(0, ssys_readfn,
ssys_writefn, s);
@ -1048,7 +1059,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
}
}
stellaris_sys_init(0x400fe000, pic[28], board);
stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr);
for (i = 0; i < 7; i++) {
if (board->dc4 & (1 << i)) {
@ -1081,6 +1092,10 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
pl022_init(0x40008000, pic[7], NULL, NULL);
}
}
if (board->dc4 & (1 << 28)) {
/* FIXME: Obey network model. */
stellaris_enet_init(&nd_table[0], 0x40048000, pic[42]);
}
if (board->peripherals & BP_GAMEPAD) {
qemu_irq gpad_irq[5];
static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };

347
hw/stellaris_enet.c Normal file
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@ -0,0 +1,347 @@
/*
* Luminary Micro Stellaris Ethernet Controller
*
* Copyright (c) 2007 CodeSourcery.
* Written by Paul Brook
*
* This code is licenced under the GPL.
*/
#include "hw.h"
#include "arm-misc.h"
#include "net.h"
#include <zlib.h>
//#define DEBUG_STELLARIS_ENET 1
#ifdef DEBUG_STELLARIS_ENET
#define DPRINTF(fmt, args...) \
do { printf("stellaris_enet: " fmt , ##args); } while (0)
#define BADF(fmt, args...) \
do { fprintf(stderr, "stellaris_enet: error: " fmt , ##args); exit(1);} while (0)
#else
#define DPRINTF(fmt, args...) do {} while(0)
#define BADF(fmt, args...) \
do { fprintf(stderr, "stellaris_enet: error: " fmt , ##args);} while (0)
#endif
#define SE_INT_RX 0x01
#define SE_INT_TXER 0x02
#define SE_INT_TXEMP 0x04
#define SE_INT_FOV 0x08
#define SE_INT_RXER 0x10
#define SE_INT_MD 0x20
#define SE_INT_PHY 0x40
#define SE_RCTL_RXEN 0x01
#define SE_RCTL_AMUL 0x02
#define SE_RCTL_PRMS 0x04
#define SE_RCTL_BADCRC 0x08
#define SE_RCTL_RSTFIFO 0x10
#define SE_TCTL_TXEN 0x01
#define SE_TCTL_PADEN 0x02
#define SE_TCTL_CRC 0x04
#define SE_TCTL_DUPLEX 0x08
typedef struct {
uint32_t base;
uint32_t ris;
uint32_t im;
uint32_t rctl;
uint32_t tctl;
uint32_t thr;
uint32_t mctl;
uint32_t mdv;
uint32_t mtxd;
uint32_t mrxd;
uint32_t np;
int tx_frame_len;
int tx_fifo_len;
uint8_t tx_fifo[2048];
/* Real hardware has a 2k fifo, which works out to be at most 31 packets.
We implement a full 31 packet fifo. */
struct {
uint8_t data[2048];
int len;
} rx[31];
uint8_t *rx_fifo;
int rx_fifo_len;
int next_packet;
VLANClientState *vc;
qemu_irq irq;
uint8_t macaddr[6];
} stellaris_enet_state;
static void stellaris_enet_update(stellaris_enet_state *s)
{
qemu_set_irq(s->irq, (s->ris & s->im) != 0);
}
/* TODO: Implement MAC address filtering. */
static void stellaris_enet_receive(void *opaque, const uint8_t *buf, int size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
int n;
uint8_t *p;
uint32_t crc;
if ((s->rctl & SE_RCTL_RXEN) == 0)
return;
if (s->np >= 31) {
DPRINTF("Packet dropped\n");
return;
}
DPRINTF("Received packet len=%d\n", size);
n = s->next_packet + s->np;
if (n >= 31)
n -= 31;
s->np++;
s->rx[n].len = size + 6;
p = s->rx[n].data;
*(p++) = (size + 6);
*(p++) = (size + 6) >> 8;
memcpy (p, buf, size);
p += size;
crc = crc32(~0, buf, size);
*(p++) = crc;
*(p++) = crc >> 8;
*(p++) = crc >> 16;
*(p++) = crc >> 24;
/* Clear the remaining bytes in the last word. */
if ((size & 3) != 2) {
memset(p, 0, (6 - size) & 3);
}
s->ris |= SE_INT_RX;
stellaris_enet_update(s);
}
static int stellaris_enet_can_receive(void *opaque)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
if ((s->rctl & SE_RCTL_RXEN) == 0)
return 1;
return (s->np < 31);
}
static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
uint32_t val;
offset -= s->base;
switch (offset) {
case 0x00: /* RIS */
DPRINTF("IRQ status %02x\n", s->ris);
return s->ris;
case 0x04: /* IM */
return s->im;
case 0x08: /* RCTL */
return s->rctl;
case 0x0c: /* TCTL */
return s->tctl;
case 0x10: /* DATA */
if (s->rx_fifo_len == 0) {
if (s->np == 0) {
BADF("RX underflow\n");
return 0;
}
s->rx_fifo_len = s->rx[s->next_packet].len;
s->rx_fifo = s->rx[s->next_packet].data;
DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
}
val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16)
| (s->rx_fifo[3] << 24);
s->rx_fifo += 4;
s->rx_fifo_len -= 4;
if (s->rx_fifo_len <= 0) {
s->rx_fifo_len = 0;
s->next_packet++;
if (s->next_packet >= 31)
s->next_packet = 0;
s->np--;
DPRINTF("RX done np=%d\n", s->np);
}
return val;
case 0x14: /* IA0 */
return s->macaddr[0] | (s->macaddr[1] << 8)
| (s->macaddr[2] << 16) | (s->macaddr[3] << 24);
case 0x18: /* IA1 */
return s->macaddr[4] | (s->macaddr[5] << 8);
case 0x1c: /* THR */
return s->thr;
case 0x20: /* MCTL */
return s->mctl;
case 0x24: /* MDV */
return s->mdv;
case 0x28: /* MADD */
return 0;
case 0x2c: /* MTXD */
return s->mtxd;
case 0x30: /* MRXD */
return s->mrxd;
case 0x34: /* NP */
return s->np;
case 0x38: /* TR */
return 0;
case 0x3c: /* Undocuented: Timestamp? */
return 0;
default:
cpu_abort (cpu_single_env, "stellaris_enet_read: Bad offset %x\n",
(int)offset);
return 0;
}
}
static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
offset -= s->base;
switch (offset) {
case 0x00: /* IACK */
s->ris &= ~value;
DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
stellaris_enet_update(s);
/* Clearing TXER also resets the TX fifo. */
if (value & SE_INT_TXER)
s->tx_frame_len = -1;
break;
case 0x04: /* IM */
DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
s->im = value;
stellaris_enet_update(s);
break;
case 0x08: /* RCTL */
s->rctl = value;
if (value & SE_RCTL_RSTFIFO) {
s->rx_fifo_len = 0;
s->np = 0;
stellaris_enet_update(s);
}
break;
case 0x0c: /* TCTL */
s->tctl = value;
break;
case 0x10: /* DATA */
if (s->tx_frame_len == -1) {
s->tx_frame_len = value & 0xffff;
if (s->tx_frame_len > 2032) {
DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
s->tx_frame_len = 0;
s->ris |= SE_INT_TXER;
stellaris_enet_update(s);
} else {
DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
/* The value written does not include the ethernet header. */
s->tx_frame_len += 14;
if ((s->tctl & SE_TCTL_CRC) == 0)
s->tx_frame_len += 4;
s->tx_fifo_len = 0;
s->tx_fifo[s->tx_fifo_len++] = value >> 16;
s->tx_fifo[s->tx_fifo_len++] = value >> 24;
}
} else {
s->tx_fifo[s->tx_fifo_len++] = value;
s->tx_fifo[s->tx_fifo_len++] = value >> 8;
s->tx_fifo[s->tx_fifo_len++] = value >> 16;
s->tx_fifo[s->tx_fifo_len++] = value >> 24;
if (s->tx_fifo_len >= s->tx_frame_len) {
/* We don't implement explicit CRC, so just chop it off. */
if ((s->tctl & SE_TCTL_CRC) == 0)
s->tx_frame_len -= 4;
if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
s->tx_fifo_len = 60;
}
qemu_send_packet(s->vc, s->tx_fifo, s->tx_frame_len);
s->tx_frame_len = -1;
s->ris |= SE_INT_TXEMP;
stellaris_enet_update(s);
DPRINTF("Done TX\n");
}
}
break;
case 0x14: /* IA0 */
s->macaddr[0] = value;
s->macaddr[1] = value >> 8;
s->macaddr[2] = value >> 16;
s->macaddr[3] = value >> 24;
break;
case 0x18: /* IA1 */
s->macaddr[4] = value;
s->macaddr[5] = value >> 8;
break;
case 0x1c: /* THR */
s->thr = value;
break;
case 0x20: /* MCTL */
s->mctl = value;
break;
case 0x24: /* MDV */
s->mdv = value;
break;
case 0x28: /* MADD */
/* ignored. */
break;
case 0x2c: /* MTXD */
s->mtxd = value & 0xff;
break;
case 0x30: /* MRXD */
case 0x34: /* NP */
case 0x38: /* TR */
/* Ignored. */
case 0x3c: /* Undocuented: Timestamp? */
/* Ignored. */
break;
default:
cpu_abort (cpu_single_env, "stellaris_enet_write: Bad offset %x\n",
(int)offset);
}
}
static CPUReadMemoryFunc *stellaris_enet_readfn[] = {
stellaris_enet_read,
stellaris_enet_read,
stellaris_enet_read
};
static CPUWriteMemoryFunc *stellaris_enet_writefn[] = {
stellaris_enet_write,
stellaris_enet_write,
stellaris_enet_write
};
static void stellaris_enet_reset(stellaris_enet_state *s)
{
s->mdv = 0x80;
s->rctl = SE_RCTL_BADCRC;
s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
| SE_INT_TXER | SE_INT_RX;
s->thr = 0x3f;
s->tx_frame_len = -1;
}
void stellaris_enet_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
stellaris_enet_state *s;
int iomemtype;
s = (stellaris_enet_state *)qemu_mallocz(sizeof(stellaris_enet_state));
iomemtype = cpu_register_io_memory(0, stellaris_enet_readfn,
stellaris_enet_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
s->base = base;
s->irq = irq;
memcpy(s->macaddr, nd->macaddr, 6);
if (nd->vlan)
s->vc = qemu_new_vlan_client(nd->vlan, stellaris_enet_receive,
stellaris_enet_can_receive, s);
stellaris_enet_reset(s);
}