VFIO update 2020-06-11
- Fix IGD split, include header to honor Kconfig (Thomas Huth) - New VMD device paravirt quirk (Jon Derrick) -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.14 (GNU/Linux) iQIcBAABAgAGBQJe4n7XAAoJECObm247sIsiBfQP/3mJJCJu/H/vfftpc1M8dpC4 MVQew0rpC5ZWRpiE2SYAF5yIVbHW83BUZIzUeO6wEhscxHQymj76gQesFrG4pt5P ZyrfEMQGym8lPYz09ZgEKQN4gCN7xBgMUc+LM/rLYCBr7CbQCNkOLjM6km7JN1aq rF8m3wNfrLVTLR33lsFXuNq3RfrxXigX/7E+v/vPh7JmqehUINc+aLzXZEAVu24v ntQqXIgWcgYQpz48aGSENfsf6oG8fUY2ZWjP4L+9+EA4SUwlLilBMXCWOHJB3v6C mQkoo+OsQ40RRzc49m8dOaSNUUXKRTwz2H+Kw/VlrxoVCU8gcWjuY+wZ536623JY zHrzih86uQRYOO2pJoqOFJ0vxvBC8ule6srupF5ZvTAO7x/JO3o2YUHUSt9amzwt TX+yh6t9NFZGmzxMvwzU0DeoHFsmRXGMOkmbWjqGPOY3bB4G1lK+tQtE5qCnLvtu A6/wHNT5BIN/YeNSoXlJuE6Ty2CpNBtzCXQ3KqkfDTbPioYs22Huxpg9GwcpBwh0 z8xHvRM020dbFDSY5T5kDnAfP7omPc/zqajDPbw9OBcQUE3B361v95sCTAeOoXef +toB3m84WlYbLHiKQBJhNUx+1eDo8qfMytkq67b47dyER/uzDCx6C7btEuFXJOJ1 IkTs9KjhL2a08hcDCeW/ =oPeB -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20200611.0' into staging VFIO update 2020-06-11 - Fix IGD split, include header to honor Kconfig (Thomas Huth) - New VMD device paravirt quirk (Jon Derrick) # gpg: Signature made Thu 11 Jun 2020 19:58:31 BST # gpg: using RSA key 239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full] # gpg: aka "Alex Williamson <alex@shazbot.org>" [full] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [full] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [full] # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-update-20200611.0: hw/vfio/pci-quirks: Fix broken legacy IGD passthrough hw/vfio: Add VMD Passthrough Quirk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
eea8f5df4e
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@ -11,6 +11,7 @@
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*/
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#include "qemu/osdep.h"
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#include "config-devices.h"
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#include "exec/memop.h"
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#include "qemu/units.h"
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#include "qemu/error-report.h"
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@ -1567,18 +1568,6 @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp)
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return 0;
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}
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int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp)
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{
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int ret;
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ret = vfio_add_nv_gpudirect_cap(vdev, errp);
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if (ret) {
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return ret;
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}
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return 0;
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}
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static void vfio_pci_nvlink2_get_tgt(Object *obj, Visitor *v,
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const char *name,
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void *opaque, Error **errp)
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@ -1709,3 +1698,75 @@ free_exit:
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return ret;
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}
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/*
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* The VMD endpoint provides a real PCIe domain to the guest and the guest
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* kernel performs enumeration of the VMD sub-device domain. Guest transactions
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* to VMD sub-devices go through MMU translation from guest addresses to
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* physical addresses. When MMIO goes to an endpoint after being translated to
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* physical addresses, the bridge rejects the transaction because the window
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* has been programmed with guest addresses.
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*
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* VMD can use the Host Physical Address in order to correctly program the
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* bridge windows in its PCIe domain. VMD device 28C0 has HPA shadow registers
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* located at offset 0x2000 in MEMBAR2 (BAR 4). This quirk provides the HPA
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* shadow registers in a vendor-specific capability register for devices
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* without native support. The position of 0xE8-0xFF is in the reserved range
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* of the VMD device capability space following the Power Management
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* Capability.
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*/
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#define VMD_SHADOW_CAP_VER 1
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#define VMD_SHADOW_CAP_LEN 24
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static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vdev, Error **errp)
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{
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uint8_t membar_phys[16];
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int ret, pos = 0xE8;
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if (!(vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, 0x201D) ||
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vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, 0x467F) ||
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vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, 0x4C3D) ||
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vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, 0x9A0B))) {
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return 0;
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}
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ret = pread(vdev->vbasedev.fd, membar_phys, 16,
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vdev->config_offset + PCI_BASE_ADDRESS_2);
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if (ret != 16) {
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error_report("VMD %s cannot read MEMBARs (%d)",
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vdev->vbasedev.name, ret);
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return -EFAULT;
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}
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ret = pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos,
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VMD_SHADOW_CAP_LEN, errp);
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if (ret < 0) {
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error_prepend(errp, "Failed to add VMD MEMBAR Shadow cap: ");
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return ret;
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}
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memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN);
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pos += PCI_CAP_FLAGS;
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pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_LEN);
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pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_VER);
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pci_set_long(vdev->pdev.config + pos, 0x53484457); /* SHDW */
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memcpy(vdev->pdev.config + pos + 4, membar_phys, 16);
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return 0;
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}
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int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp)
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{
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int ret;
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ret = vfio_add_nv_gpudirect_cap(vdev, errp);
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if (ret) {
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return ret;
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}
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ret = vfio_add_vmd_shadow_cap(vdev, errp);
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if (ret) {
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return ret;
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}
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return 0;
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}
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