accel/tcg: demacro cputlb
Instead of expanding a series of macros to generate the load/store helpers we move stuff into common functions and rely on the compiler to eliminate the dead code for each variant. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Alex Bennée
parent
a6ae23831b
commit
eed5664238
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@ -1168,26 +1168,421 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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# define TGT_BE(X) (X)
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# define TGT_LE(X) BSWAP(X)
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#define NEED_BE_BSWAP 0
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#define NEED_LE_BSWAP 1
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#else
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# define TGT_BE(X) BSWAP(X)
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# define TGT_LE(X) (X)
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#define NEED_BE_BSWAP 1
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#define NEED_LE_BSWAP 0
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#endif
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#define MMUSUFFIX _mmu
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/*
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* Byte Swap Helper
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*
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* This should all dead code away depending on the build host and
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* access type.
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*/
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#define DATA_SIZE 1
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#include "softmmu_template.h"
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static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endian)
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{
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if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) {
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switch (size) {
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case 1: return val;
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case 2: return bswap16(val);
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case 4: return bswap32(val);
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case 8: return bswap64(val);
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default:
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g_assert_not_reached();
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}
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} else {
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return val;
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}
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}
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#define DATA_SIZE 2
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#include "softmmu_template.h"
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/*
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* Load Helpers
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*
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* We support two different access types. SOFTMMU_CODE_ACCESS is
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* specifically for reading instructions from system memory. It is
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* called by the translation loop and in some helpers where the code
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* is disassembled. It shouldn't be called directly by guest code.
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*/
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#define DATA_SIZE 4
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#include "softmmu_template.h"
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static uint64_t load_helper(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr,
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size_t size, bool big_endian,
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bool code_read)
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{
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uintptr_t mmu_idx = get_mmuidx(oi);
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uintptr_t index = tlb_index(env, mmu_idx, addr);
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CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
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target_ulong tlb_addr = code_read ? entry->addr_code : entry->addr_read;
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const size_t tlb_off = code_read ?
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offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read);
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unsigned a_bits = get_alignment_bits(get_memop(oi));
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void *haddr;
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uint64_t res;
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#define DATA_SIZE 8
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#include "softmmu_template.h"
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/* Handle CPU specific unaligned behaviour */
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr,
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code_read ? MMU_INST_FETCH : MMU_DATA_LOAD,
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mmu_idx, retaddr);
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}
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/* If the TLB entry is for a different page, reload and try again. */
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if (!tlb_hit(tlb_addr, addr)) {
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if (!victim_tlb_hit(env, mmu_idx, index, tlb_off,
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addr & TARGET_PAGE_MASK)) {
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tlb_fill(ENV_GET_CPU(env), addr, size,
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code_read ? MMU_INST_FETCH : MMU_DATA_LOAD,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = code_read ? entry->addr_code : entry->addr_read;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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uint64_t tmp;
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if ((addr & (size - 1)) != 0) {
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goto do_unaligned_access;
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}
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tmp = io_readx(env, iotlbentry, mmu_idx, addr, retaddr,
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tlb_addr & TLB_RECHECK,
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code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, size);
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return handle_bswap(tmp, size, big_endian);
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (size > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + size - 1
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
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tcg_target_ulong r1, r2;
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unsigned shift;
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do_unaligned_access:
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addr1 = addr & ~(size - 1);
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addr2 = addr1 + size;
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r1 = load_helper(env, addr1, oi, retaddr, size, big_endian, code_read);
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r2 = load_helper(env, addr2, oi, retaddr, size, big_endian, code_read);
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shift = (addr & (size - 1)) * 8;
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if (big_endian) {
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/* Big-endian combine. */
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res = (r1 << shift) | (r2 >> ((size * 8) - shift));
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} else {
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/* Little-endian combine. */
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res = (r1 >> shift) | (r2 << ((size * 8) - shift));
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}
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return res & MAKE_64BIT_MASK(0, size * 8);
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}
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haddr = (void *)((uintptr_t)addr + entry->addend);
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switch (size) {
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case 1:
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res = ldub_p(haddr);
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break;
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case 2:
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if (big_endian) {
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res = lduw_be_p(haddr);
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} else {
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res = lduw_le_p(haddr);
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}
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break;
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case 4:
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if (big_endian) {
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res = (uint32_t)ldl_be_p(haddr);
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} else {
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res = (uint32_t)ldl_le_p(haddr);
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}
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break;
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case 8:
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if (big_endian) {
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res = ldq_be_p(haddr);
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} else {
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res = ldq_le_p(haddr);
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}
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break;
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default:
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g_assert_not_reached();
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}
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return res;
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}
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/*
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* For the benefit of TCG generated code, we want to avoid the
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* complication of ABI-specific return type promotion and always
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* return a value extended to the register size of the host. This is
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* tcg_target_long, except in the case of a 32-bit host and 64-bit
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* data, and for that we always have uint64_t.
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*
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* We don't bother with this widened value for SOFTMMU_CODE_ACCESS.
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*/
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tcg_target_ulong __attribute__((flatten))
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helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, 1, false, false);
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}
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tcg_target_ulong __attribute__((flatten))
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helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, 2, false, false);
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}
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tcg_target_ulong __attribute__((flatten))
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helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, 2, true, false);
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}
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tcg_target_ulong __attribute__((flatten))
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helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, 4, false, false);
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}
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tcg_target_ulong __attribute__((flatten))
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helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, 4, true, false);
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}
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uint64_t __attribute__((flatten))
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helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, 8, false, false);
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}
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uint64_t __attribute__((flatten))
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helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
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uintptr_t retaddr)
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{
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return load_helper(env, addr, oi, retaddr, 8, true, false);
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}
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/*
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* Provide signed versions of the load routines as well. We can of course
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* avoid this for 64-bit data, or for 32-bit data on 32-bit host.
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*/
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tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr);
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}
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/*
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* Store Helpers
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*/
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static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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TCGMemOpIdx oi, uintptr_t retaddr, size_t size,
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bool big_endian)
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{
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uintptr_t mmu_idx = get_mmuidx(oi);
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uintptr_t index = tlb_index(env, mmu_idx, addr);
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CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
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target_ulong tlb_addr = tlb_addr_write(entry);
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const size_t tlb_off = offsetof(CPUTLBEntry, addr_write);
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unsigned a_bits = get_alignment_bits(get_memop(oi));
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void *haddr;
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/* Handle CPU specific unaligned behaviour */
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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/* If the TLB entry is for a different page, reload and try again. */
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if (!tlb_hit(tlb_addr, addr)) {
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if (!victim_tlb_hit(env, mmu_idx, index, tlb_off,
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addr & TARGET_PAGE_MASK)) {
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tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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if ((addr & (size - 1)) != 0) {
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goto do_unaligned_access;
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}
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io_writex(env, iotlbentry, mmu_idx,
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handle_bswap(val, size, big_endian),
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addr, retaddr, tlb_addr & TLB_RECHECK, size);
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return;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (size > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + size - 1
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>= TARGET_PAGE_SIZE)) {
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int i;
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uintptr_t index2;
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CPUTLBEntry *entry2;
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target_ulong page2, tlb_addr2;
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do_unaligned_access:
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/*
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* Ensure the second page is in the TLB. Note that the first page
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* is already guaranteed to be filled, and that the second page
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* cannot evict the first.
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*/
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page2 = (addr + size) & TARGET_PAGE_MASK;
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index2 = tlb_index(env, mmu_idx, page2);
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entry2 = tlb_entry(env, mmu_idx, page2);
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tlb_addr2 = tlb_addr_write(entry2);
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if (!tlb_hit_page(tlb_addr2, page2)
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&& !victim_tlb_hit(env, mmu_idx, index2, tlb_off,
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page2 & TARGET_PAGE_MASK)) {
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tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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/*
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* XXX: not efficient, but simple.
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* This loop must go in the forward direction to avoid issues
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* with self-modifying code in Windows 64-bit.
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*/
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for (i = 0; i < size; ++i) {
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uint8_t val8;
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if (big_endian) {
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/* Big-endian extract. */
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val8 = val >> (((size - 1) * 8) - (i * 8));
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} else {
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/* Little-endian extract. */
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val8 = val >> (i * 8);
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}
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store_helper(env, addr + i, val8, oi, retaddr, 1, big_endian);
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}
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return;
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}
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haddr = (void *)((uintptr_t)addr + entry->addend);
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switch (size) {
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case 1:
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stb_p(haddr, val);
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break;
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case 2:
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if (big_endian) {
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stw_be_p(haddr, val);
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} else {
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stw_le_p(haddr, val);
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}
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break;
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case 4:
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if (big_endian) {
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stl_be_p(haddr, val);
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} else {
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stl_le_p(haddr, val);
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}
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break;
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case 8:
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if (big_endian) {
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stq_be_p(haddr, val);
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} else {
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stq_le_p(haddr, val);
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}
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break;
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default:
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g_assert_not_reached();
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break;
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}
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}
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void __attribute__((flatten))
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helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, 1, false);
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}
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void __attribute__((flatten))
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helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, 2, false);
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}
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void __attribute__((flatten))
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helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, 2, true);
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}
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void __attribute__((flatten))
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helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, 4, false);
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}
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void __attribute__((flatten))
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helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, 4, true);
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}
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void __attribute__((flatten))
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helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, 8, false);
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}
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void __attribute__((flatten))
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helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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store_helper(env, addr, val, oi, retaddr, 8, true);
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}
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/* First set of helpers allows passing in of OI and RETADDR. This makes
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them callable from other helpers. */
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@ -1248,20 +1643,51 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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/* Code access functions. */
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#undef MMUSUFFIX
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#define MMUSUFFIX _cmmu
|
||||
#undef GETPC
|
||||
#define GETPC() ((uintptr_t)0)
|
||||
#define SOFTMMU_CODE_ACCESS
|
||||
uint8_t __attribute__((flatten))
|
||||
helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
|
||||
uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, 1, false, true);
|
||||
}
|
||||
|
||||
#define DATA_SIZE 1
|
||||
#include "softmmu_template.h"
|
||||
uint16_t __attribute__((flatten))
|
||||
helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
|
||||
uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, 2, false, true);
|
||||
}
|
||||
|
||||
#define DATA_SIZE 2
|
||||
#include "softmmu_template.h"
|
||||
uint16_t __attribute__((flatten))
|
||||
helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
|
||||
uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, 2, true, true);
|
||||
}
|
||||
|
||||
#define DATA_SIZE 4
|
||||
#include "softmmu_template.h"
|
||||
uint32_t __attribute__((flatten))
|
||||
helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
|
||||
uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, 4, false, true);
|
||||
}
|
||||
|
||||
#define DATA_SIZE 8
|
||||
#include "softmmu_template.h"
|
||||
uint32_t __attribute__((flatten))
|
||||
helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
|
||||
uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, 4, true, true);
|
||||
}
|
||||
|
||||
uint64_t __attribute__((flatten))
|
||||
helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
|
||||
uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, 8, false, true);
|
||||
}
|
||||
|
||||
uint64_t __attribute__((flatten))
|
||||
helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
|
||||
uintptr_t retaddr)
|
||||
{
|
||||
return load_helper(env, addr, oi, retaddr, 8, true, true);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,454 +0,0 @@
|
|||
/*
|
||||
* Software MMU support
|
||||
*
|
||||
* Generate helpers used by TCG for qemu_ld/st ops and code load
|
||||
* functions.
|
||||
*
|
||||
* Included from target op helpers and exec.c.
|
||||
*
|
||||
* Copyright (c) 2003 Fabrice Bellard
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#if DATA_SIZE == 8
|
||||
#define SUFFIX q
|
||||
#define LSUFFIX q
|
||||
#define SDATA_TYPE int64_t
|
||||
#define DATA_TYPE uint64_t
|
||||
#elif DATA_SIZE == 4
|
||||
#define SUFFIX l
|
||||
#define LSUFFIX l
|
||||
#define SDATA_TYPE int32_t
|
||||
#define DATA_TYPE uint32_t
|
||||
#elif DATA_SIZE == 2
|
||||
#define SUFFIX w
|
||||
#define LSUFFIX uw
|
||||
#define SDATA_TYPE int16_t
|
||||
#define DATA_TYPE uint16_t
|
||||
#elif DATA_SIZE == 1
|
||||
#define SUFFIX b
|
||||
#define LSUFFIX ub
|
||||
#define SDATA_TYPE int8_t
|
||||
#define DATA_TYPE uint8_t
|
||||
#else
|
||||
#error unsupported data size
|
||||
#endif
|
||||
|
||||
|
||||
/* For the benefit of TCG generated code, we want to avoid the complication
|
||||
of ABI-specific return type promotion and always return a value extended
|
||||
to the register size of the host. This is tcg_target_long, except in the
|
||||
case of a 32-bit host and 64-bit data, and for that we always have
|
||||
uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
|
||||
#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
|
||||
# define WORD_TYPE DATA_TYPE
|
||||
# define USUFFIX SUFFIX
|
||||
#else
|
||||
# define WORD_TYPE tcg_target_ulong
|
||||
# define USUFFIX glue(u, SUFFIX)
|
||||
# define SSUFFIX glue(s, SUFFIX)
|
||||
#endif
|
||||
|
||||
#ifdef SOFTMMU_CODE_ACCESS
|
||||
#define READ_ACCESS_TYPE MMU_INST_FETCH
|
||||
#define ADDR_READ addr_code
|
||||
#else
|
||||
#define READ_ACCESS_TYPE MMU_DATA_LOAD
|
||||
#define ADDR_READ addr_read
|
||||
#endif
|
||||
|
||||
#if DATA_SIZE == 8
|
||||
# define BSWAP(X) bswap64(X)
|
||||
#elif DATA_SIZE == 4
|
||||
# define BSWAP(X) bswap32(X)
|
||||
#elif DATA_SIZE == 2
|
||||
# define BSWAP(X) bswap16(X)
|
||||
#else
|
||||
# define BSWAP(X) (X)
|
||||
#endif
|
||||
|
||||
#if DATA_SIZE == 1
|
||||
# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
|
||||
# define helper_be_ld_name helper_le_ld_name
|
||||
# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
|
||||
# define helper_be_lds_name helper_le_lds_name
|
||||
# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
|
||||
# define helper_be_st_name helper_le_st_name
|
||||
#else
|
||||
# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
|
||||
# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
|
||||
# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
|
||||
# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
|
||||
# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
|
||||
# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
|
||||
#endif
|
||||
|
||||
#ifndef SOFTMMU_CODE_ACCESS
|
||||
static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
|
||||
size_t mmu_idx, size_t index,
|
||||
target_ulong addr,
|
||||
uintptr_t retaddr,
|
||||
bool recheck,
|
||||
MMUAccessType access_type)
|
||||
{
|
||||
CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
|
||||
return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck,
|
||||
access_type, DATA_SIZE);
|
||||
}
|
||||
#endif
|
||||
|
||||
WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
uintptr_t mmu_idx = get_mmuidx(oi);
|
||||
uintptr_t index = tlb_index(env, mmu_idx, addr);
|
||||
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
|
||||
target_ulong tlb_addr = entry->ADDR_READ;
|
||||
unsigned a_bits = get_alignment_bits(get_memop(oi));
|
||||
uintptr_t haddr;
|
||||
DATA_TYPE res;
|
||||
|
||||
if (addr & ((1 << a_bits) - 1)) {
|
||||
cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
|
||||
mmu_idx, retaddr);
|
||||
}
|
||||
|
||||
/* If the TLB entry is for a different page, reload and try again. */
|
||||
if (!tlb_hit(tlb_addr, addr)) {
|
||||
if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
|
||||
tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
|
||||
mmu_idx, retaddr);
|
||||
index = tlb_index(env, mmu_idx, addr);
|
||||
entry = tlb_entry(env, mmu_idx, addr);
|
||||
}
|
||||
tlb_addr = entry->ADDR_READ;
|
||||
}
|
||||
|
||||
/* Handle an IO access. */
|
||||
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
|
||||
if ((addr & (DATA_SIZE - 1)) != 0) {
|
||||
goto do_unaligned_access;
|
||||
}
|
||||
|
||||
/* ??? Note that the io helpers always read data in the target
|
||||
byte ordering. We should push the LE/BE request down into io. */
|
||||
res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr,
|
||||
tlb_addr & TLB_RECHECK,
|
||||
READ_ACCESS_TYPE);
|
||||
res = TGT_LE(res);
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Handle slow unaligned access (it spans two pages or IO). */
|
||||
if (DATA_SIZE > 1
|
||||
&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
|
||||
>= TARGET_PAGE_SIZE)) {
|
||||
target_ulong addr1, addr2;
|
||||
DATA_TYPE res1, res2;
|
||||
unsigned shift;
|
||||
do_unaligned_access:
|
||||
addr1 = addr & ~(DATA_SIZE - 1);
|
||||
addr2 = addr1 + DATA_SIZE;
|
||||
res1 = helper_le_ld_name(env, addr1, oi, retaddr);
|
||||
res2 = helper_le_ld_name(env, addr2, oi, retaddr);
|
||||
shift = (addr & (DATA_SIZE - 1)) * 8;
|
||||
|
||||
/* Little-endian combine. */
|
||||
res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
|
||||
return res;
|
||||
}
|
||||
|
||||
haddr = addr + entry->addend;
|
||||
#if DATA_SIZE == 1
|
||||
res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
|
||||
#else
|
||||
res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
#if DATA_SIZE > 1
|
||||
WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
uintptr_t mmu_idx = get_mmuidx(oi);
|
||||
uintptr_t index = tlb_index(env, mmu_idx, addr);
|
||||
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
|
||||
target_ulong tlb_addr = entry->ADDR_READ;
|
||||
unsigned a_bits = get_alignment_bits(get_memop(oi));
|
||||
uintptr_t haddr;
|
||||
DATA_TYPE res;
|
||||
|
||||
if (addr & ((1 << a_bits) - 1)) {
|
||||
cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
|
||||
mmu_idx, retaddr);
|
||||
}
|
||||
|
||||
/* If the TLB entry is for a different page, reload and try again. */
|
||||
if (!tlb_hit(tlb_addr, addr)) {
|
||||
if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
|
||||
tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
|
||||
mmu_idx, retaddr);
|
||||
index = tlb_index(env, mmu_idx, addr);
|
||||
entry = tlb_entry(env, mmu_idx, addr);
|
||||
}
|
||||
tlb_addr = entry->ADDR_READ;
|
||||
}
|
||||
|
||||
/* Handle an IO access. */
|
||||
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
|
||||
if ((addr & (DATA_SIZE - 1)) != 0) {
|
||||
goto do_unaligned_access;
|
||||
}
|
||||
|
||||
/* ??? Note that the io helpers always read data in the target
|
||||
byte ordering. We should push the LE/BE request down into io. */
|
||||
res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr,
|
||||
tlb_addr & TLB_RECHECK,
|
||||
READ_ACCESS_TYPE);
|
||||
res = TGT_BE(res);
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Handle slow unaligned access (it spans two pages or IO). */
|
||||
if (DATA_SIZE > 1
|
||||
&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
|
||||
>= TARGET_PAGE_SIZE)) {
|
||||
target_ulong addr1, addr2;
|
||||
DATA_TYPE res1, res2;
|
||||
unsigned shift;
|
||||
do_unaligned_access:
|
||||
addr1 = addr & ~(DATA_SIZE - 1);
|
||||
addr2 = addr1 + DATA_SIZE;
|
||||
res1 = helper_be_ld_name(env, addr1, oi, retaddr);
|
||||
res2 = helper_be_ld_name(env, addr2, oi, retaddr);
|
||||
shift = (addr & (DATA_SIZE - 1)) * 8;
|
||||
|
||||
/* Big-endian combine. */
|
||||
res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
|
||||
return res;
|
||||
}
|
||||
|
||||
haddr = addr + entry->addend;
|
||||
res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
|
||||
return res;
|
||||
}
|
||||
#endif /* DATA_SIZE > 1 */
|
||||
|
||||
#ifndef SOFTMMU_CODE_ACCESS
|
||||
|
||||
/* Provide signed versions of the load routines as well. We can of course
|
||||
avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
|
||||
#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
|
||||
WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr);
|
||||
}
|
||||
|
||||
# if DATA_SIZE > 1
|
||||
WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr);
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
||||
static inline void glue(io_write, SUFFIX)(CPUArchState *env,
|
||||
size_t mmu_idx, size_t index,
|
||||
DATA_TYPE val,
|
||||
target_ulong addr,
|
||||
uintptr_t retaddr,
|
||||
bool recheck)
|
||||
{
|
||||
CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
|
||||
return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr,
|
||||
recheck, DATA_SIZE);
|
||||
}
|
||||
|
||||
void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
uintptr_t mmu_idx = get_mmuidx(oi);
|
||||
uintptr_t index = tlb_index(env, mmu_idx, addr);
|
||||
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
|
||||
target_ulong tlb_addr = tlb_addr_write(entry);
|
||||
unsigned a_bits = get_alignment_bits(get_memop(oi));
|
||||
uintptr_t haddr;
|
||||
|
||||
if (addr & ((1 << a_bits) - 1)) {
|
||||
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
||||
mmu_idx, retaddr);
|
||||
}
|
||||
|
||||
/* If the TLB entry is for a different page, reload and try again. */
|
||||
if (!tlb_hit(tlb_addr, addr)) {
|
||||
if (!VICTIM_TLB_HIT(addr_write, addr)) {
|
||||
tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
|
||||
mmu_idx, retaddr);
|
||||
index = tlb_index(env, mmu_idx, addr);
|
||||
entry = tlb_entry(env, mmu_idx, addr);
|
||||
}
|
||||
tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;
|
||||
}
|
||||
|
||||
/* Handle an IO access. */
|
||||
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
|
||||
if ((addr & (DATA_SIZE - 1)) != 0) {
|
||||
goto do_unaligned_access;
|
||||
}
|
||||
|
||||
/* ??? Note that the io helpers always read data in the target
|
||||
byte ordering. We should push the LE/BE request down into io. */
|
||||
val = TGT_LE(val);
|
||||
glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr,
|
||||
retaddr, tlb_addr & TLB_RECHECK);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Handle slow unaligned access (it spans two pages or IO). */
|
||||
if (DATA_SIZE > 1
|
||||
&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
|
||||
>= TARGET_PAGE_SIZE)) {
|
||||
int i;
|
||||
target_ulong page2;
|
||||
CPUTLBEntry *entry2;
|
||||
do_unaligned_access:
|
||||
/* Ensure the second page is in the TLB. Note that the first page
|
||||
is already guaranteed to be filled, and that the second page
|
||||
cannot evict the first. */
|
||||
page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
|
||||
entry2 = tlb_entry(env, mmu_idx, page2);
|
||||
if (!tlb_hit_page(tlb_addr_write(entry2), page2)
|
||||
&& !VICTIM_TLB_HIT(addr_write, page2)) {
|
||||
tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,
|
||||
mmu_idx, retaddr);
|
||||
}
|
||||
|
||||
/* XXX: not efficient, but simple. */
|
||||
/* This loop must go in the forward direction to avoid issues
|
||||
with self-modifying code in Windows 64-bit. */
|
||||
for (i = 0; i < DATA_SIZE; ++i) {
|
||||
/* Little-endian extract. */
|
||||
uint8_t val8 = val >> (i * 8);
|
||||
glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
|
||||
oi, retaddr);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
haddr = addr + entry->addend;
|
||||
#if DATA_SIZE == 1
|
||||
glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
|
||||
#else
|
||||
glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if DATA_SIZE > 1
|
||||
void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
uintptr_t mmu_idx = get_mmuidx(oi);
|
||||
uintptr_t index = tlb_index(env, mmu_idx, addr);
|
||||
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
|
||||
target_ulong tlb_addr = tlb_addr_write(entry);
|
||||
unsigned a_bits = get_alignment_bits(get_memop(oi));
|
||||
uintptr_t haddr;
|
||||
|
||||
if (addr & ((1 << a_bits) - 1)) {
|
||||
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
||||
mmu_idx, retaddr);
|
||||
}
|
||||
|
||||
/* If the TLB entry is for a different page, reload and try again. */
|
||||
if (!tlb_hit(tlb_addr, addr)) {
|
||||
if (!VICTIM_TLB_HIT(addr_write, addr)) {
|
||||
tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
|
||||
mmu_idx, retaddr);
|
||||
index = tlb_index(env, mmu_idx, addr);
|
||||
entry = tlb_entry(env, mmu_idx, addr);
|
||||
}
|
||||
tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;
|
||||
}
|
||||
|
||||
/* Handle an IO access. */
|
||||
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
|
||||
if ((addr & (DATA_SIZE - 1)) != 0) {
|
||||
goto do_unaligned_access;
|
||||
}
|
||||
|
||||
/* ??? Note that the io helpers always read data in the target
|
||||
byte ordering. We should push the LE/BE request down into io. */
|
||||
val = TGT_BE(val);
|
||||
glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr,
|
||||
tlb_addr & TLB_RECHECK);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Handle slow unaligned access (it spans two pages or IO). */
|
||||
if (DATA_SIZE > 1
|
||||
&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
|
||||
>= TARGET_PAGE_SIZE)) {
|
||||
int i;
|
||||
target_ulong page2;
|
||||
CPUTLBEntry *entry2;
|
||||
do_unaligned_access:
|
||||
/* Ensure the second page is in the TLB. Note that the first page
|
||||
is already guaranteed to be filled, and that the second page
|
||||
cannot evict the first. */
|
||||
page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
|
||||
entry2 = tlb_entry(env, mmu_idx, page2);
|
||||
if (!tlb_hit_page(tlb_addr_write(entry2), page2)
|
||||
&& !VICTIM_TLB_HIT(addr_write, page2)) {
|
||||
tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,
|
||||
mmu_idx, retaddr);
|
||||
}
|
||||
|
||||
/* XXX: not efficient, but simple */
|
||||
/* This loop must go in the forward direction to avoid issues
|
||||
with self-modifying code. */
|
||||
for (i = 0; i < DATA_SIZE; ++i) {
|
||||
/* Big-endian extract. */
|
||||
uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
|
||||
glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
|
||||
oi, retaddr);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
haddr = addr + entry->addend;
|
||||
glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
|
||||
}
|
||||
#endif /* DATA_SIZE > 1 */
|
||||
#endif /* !defined(SOFTMMU_CODE_ACCESS) */
|
||||
|
||||
#undef READ_ACCESS_TYPE
|
||||
#undef DATA_TYPE
|
||||
#undef SUFFIX
|
||||
#undef LSUFFIX
|
||||
#undef DATA_SIZE
|
||||
#undef ADDR_READ
|
||||
#undef WORD_TYPE
|
||||
#undef SDATA_TYPE
|
||||
#undef USUFFIX
|
||||
#undef SSUFFIX
|
||||
#undef BSWAP
|
||||
#undef helper_le_ld_name
|
||||
#undef helper_be_ld_name
|
||||
#undef helper_le_lds_name
|
||||
#undef helper_be_lds_name
|
||||
#undef helper_le_st_name
|
||||
#undef helper_be_st_name
|
||||
Loading…
Reference in New Issue